[coreboot-gerrit] Change in coreboot[master]: nb/intel/nehalem: Disable PEG and IGD based on devicetree

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35744 )

Change subject: nb/intel/nehalem: Disable PEG and IGD based on devicetree
......................................................................

nb/intel/nehalem: Disable PEG and IGD based on devicetree

Tested on Thinkpad X201: PEG device hidden.

Change-Id: Ib378458a55e18cc02fc49b3e6d6939d31dd4aa65
Signed-off-by: Arthur Heymans 
---
M src/mainboard/lenovo/x201/devicetree.cb
M src/mainboard/packardbell/ms2290/devicetree.cb
M src/northbridge/intel/nehalem/nehalem.h
M src/northbridge/intel/nehalem/northbridge.c
4 files changed, 27 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/35744/1

diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb
index bf74d71..de6d568 100644
--- a/src/mainboard/lenovo/x201/devicetree.cb
+++ b/src/mainboard/lenovo/x201/devicetree.cb
@@ -48,6 +48,7 @@
    	device pci 00.0 on # Host bridge
    		subsystemid 0x17aa 0x2193
    	end
+		device pci 01.0 off end # PEG
    	device pci 02.0 on # VGA controller
    		subsystemid 0x17aa 0x215a
    	end
diff --git a/src/mainboard/packardbell/ms2290/devicetree.cb b/src/mainboard/packardbell/ms2290/devicetree.cb
index bb4e854..c98f9a3 100644
--- a/src/mainboard/packardbell/ms2290/devicetree.cb
+++ b/src/mainboard/packardbell/ms2290/devicetree.cb
@@ -48,6 +48,7 @@
    	device pci 00.0 on # Host bridge
    		subsystemid 0x1025 0x0379
    	end
+		device pci 01.0 off end # PEG
    	device pci 02.0 on # VGA controller
    		subsystemid 0x1025 0x0379
    	end
diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h
index 22bf596..d7646e4 100644
--- a/src/northbridge/intel/nehalem/nehalem.h
+++ b/src/northbridge/intel/nehalem/nehalem.h
@@ -67,8 +67,6 @@
 #define D0F0_MCHBAR_HI 0x4c
 #define D0F0_GGC 0x52
 #define D0F0_DEVEN 0x54
-/* Note: Intel's datasheet is broken. Assume the following values are correct */
-#define  DEVEN_PEG60	(1 << 13)
 #define  DEVEN_IGD	(1 << 3)
 #define  DEVEN_PEG10	(1 << 1)
 #define  DEVEN_HOST	(1 << 0)
diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c
index 7b9283f..fea6c7b 100644
--- a/src/northbridge/intel/nehalem/northbridge.c
+++ b/src/northbridge/intel/nehalem/northbridge.c
@@ -224,9 +224,34 @@
    DMIBAR32(0x88) = reg32;
 }

+/* Disable unused PEG devices based on devicetree */
+static void disable_peg_igd(void)
+{
+	struct device *dev;
+	u32 reg;
+
+	dev = pcidev_on_root(0, 0);
+	reg = pci_read_config32(dev, D0F0_DEVEN);
+
+	dev = pcidev_on_root(1, 0);
+	if (!dev || !dev->enabled) {
+		printk(BIOS_DEBUG, "Disabling PEG10.\n");
+		reg &= ~DEVEN_PEG10;
+	}
+	dev = pcidev_on_root(2, 0);
+	if (!dev || !dev->enabled) {
+		printk(BIOS_DEBUG, "Disabling IGD.\n");
+		reg &= ~DEVEN_IGD;
+	}
+	dev = pcidev_on_root(0, 0);
+	pci_write_config32(dev, D0F0_DEVEN, reg);
+}
+
 static void northbridge_init(struct device *dev)
 {
    northbridge_dmi_init(dev);
+
+	disable_peg_igd();
 }

static struct pci_operations intel_pci_ops = {