[coreboot-gerrit] Change in coreboot[master]: src/southbridge/amd/pi/hudson: add southbridge C bootblock initializa...

[Michał Żygowski (Code Review)]

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37168 )

Change subject: src/southbridge/amd/pi/hudson: add southbridge C bootblock initialization
......................................................................

src/southbridge/amd/pi/hudson: add southbridge C bootblock initialization

Signed-off-by: Michał Żygowski 
Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af
---
M src/southbridge/amd/pi/hudson/Makefile.inc
M src/southbridge/amd/pi/hudson/bootblock.c
M src/southbridge/amd/pi/hudson/hudson.h
3 files changed, 55 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/37168/1

diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc
index 0eccadb..8c47328 100644
--- a/src/southbridge/amd/pi/hudson/Makefile.inc
+++ b/src/southbridge/amd/pi/hudson/Makefile.inc
@@ -28,7 +28,12 @@
 #
 #*****************************************************************************

-bootblock-y += enable_usbdebug.c
+
+ifeq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y)
+bootblock-y += bootblock.c
+bootblock-y += early_setup.c
+bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c
+endif

romstage-y += early_setup.c
 romstage-y += enable_usbdebug.c
diff --git a/src/southbridge/amd/pi/hudson/bootblock.c b/src/southbridge/amd/pi/hudson/bootblock.c
index f12cec8..d5faeb3 100644
--- a/src/southbridge/amd/pi/hudson/bootblock.c
+++ b/src/southbridge/amd/pi/hudson/bootblock.c
@@ -60,3 +60,48 @@
 {
    hudson_enable_rom();
 }
+
+#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
+
+#include <bootblock_common.h>
+#include <arch/io.h>
+#include <device/pci_ids.h>
+#include <southbridge/amd/pi/hudson/hudson.h>
+
+void bootblock_soc_early_init(void)
+{
+	pci_devfn_t dev;
+	u32 data;
+
+	bootblock_southbridge_init();
+	hudson_lpc_decode();
+
+	dev = PCI_DEV(0, 0x14, 3);
+	data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE);
+	/* enable 0x2e/0x4e IO decoding for SuperIO */
+	pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3);
+
+	/*
+	 * Enable FCH to decode TPM associated Memory and IO regions for vboot
+	 *
+	 * Enable decoding of TPM cycles defined in TPM 1.2 spec
+	 * Enable decoding of legacy TPM addresses: IO addresses 0x7f-
+	 * 0x7e and 0xef-0xee.
+	 */
+
+	data = pci_read_config32(dev, LPC_TRUSTED_PLATFORM_MODULE);
+	data |= TPM_12_EN | TPM_LEGACY_EN;
+	pci_write_config32(dev, LPC_TRUSTED_PLATFORM_MODULE, data);
+
+	/*
+	 *  In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
+	 *  LpcClk[1:0]".  This following register setting has been
+	 *  replicated in every reference design since Parmer, so it is
+	 *  believed to be required even though it is not documented in
+	 *  the SoC BKDGs.  Without this setting, there is no serial
+	 *  output.
+	 */
+	outb(0xd2, 0xcd6);
+	outb(0x00, 0xcd7);
+}
+#endif
diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h
index 9511a6a..08adb84 100644
--- a/src/southbridge/amd/pi/hudson/hudson.h
+++ b/src/southbridge/amd/pi/hudson/hudson.h
@@ -117,6 +117,10 @@
 #define   LPC_ALT_WIDEIO1_ENABLE	BIT(2)
 #define   LPC_ALT_WIDEIO0_ENABLE	BIT(0)

+#define LPC_TRUSTED_PLATFORM_MODULE	0x7c
+#define   TPM_12_EN			BIT(0)
+#define   TPM_LEGACY_EN			BIT(2)
+
 #define LPC_WIDEIO2_GENERIC_PORT	0x90

#define SPI_CNTRL0			0x00