Máté Kukri has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44092 )
Change subject: soc/intel/baytrail: Add MRC SMBus workaround ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44092/4/src/soc/intel/baytrail/roms... File src/soc/intel/baytrail/romstage/raminit.c:
https://review.coreboot.org/c/coreboot/+/44092/4/src/soc/intel/baytrail/roms... PS4, Line 170: if (mp->mainboard.spd_addrs[i]) { : i2c_eeprom_read(mp->mainboard.spd_addrs[i], : 0, SPD_SIZE, spd_buf[i]); : /* NOTE: the MRC expects both SPD pointers : to match */ : mp->mainboard.dram_data[i] = spd_buf; : }
So a DIMM in only channel 1 would never boot? Same for different DIMM's? I'd print some warning abou […]
A single DIMM in channel 1 would surely fail. (I assume) Different DIMMs might work if the one in channel 1 can work with the same timings as the one in channel 0, even if the default its SPD reports does not match. Just a sidenote: This (https://imgur.com/6yuhHRR) is the only code inside the MRC I can find that directly touches the passed in SPD pointers, and to me it looks like different pointers would work, but I don't have a two channel board to test. And Angel said it won't work on his Q1900 so I went with this fix.