Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69203 )
Change subject: commonlib: Reserve 0x50-0x5f postcodes for SoC/CPU/chipset ......................................................................
commonlib: Reserve 0x50-0x5f postcodes for SoC/CPU/chipset
Postcodes 0x50 to 0x5f are currently unallocated in post_codes.h. Reserve these values for SoC use. SoCs are currently using a variety of different values, so should be moved into this range where possible.
If for some reason, the SoC vendors don't want to use this range, I'm fine with that, but this is the range that there shouldn't be conflicts with other coreboot codes.
Signed-off-by: Martin Roth gaumless@gmail.com Change-Id: Ic9eeb05f66b66899b8471215c38af54eda816c8a --- M src/commonlib/include/commonlib/console/post_codes.h 1 file changed, 43 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/69203/1
diff --git a/src/commonlib/include/commonlib/console/post_codes.h b/src/commonlib/include/commonlib/console/post_codes.h index d838815..7513595 100644 --- a/src/commonlib/include/commonlib/console/post_codes.h +++ b/src/commonlib/include/commonlib/console/post_codes.h @@ -111,6 +111,31 @@ #define POST_CONSOLE_BOOT_MSG 0x40
/** + * @brief SoC/CPU/Chipset reserved postcodes + * + * The postcodes 0x50 to 0x5f are reserved for SoC specific functions. + * While there is no restriction on how these are used, it is recommended + * that the general flow be from lower values to higher values. It is + * further recommended that 0x5f be used if there is a fatal error. + */ +#define POST_SOC_SPECIFIC_0 0x50 +#define POST_SOC_SPECIFIC_1 0x51 +#define POST_SOC_SPECIFIC_2 0x52 +#define POST_SOC_SPECIFIC_3 0x53 +#define POST_SOC_SPECIFIC_4 0x54 +#define POST_SOC_SPECIFIC_5 0x55 +#define POST_SOC_SPECIFIC_6 0x56 +#define POST_SOC_SPECIFIC_7 0x57 +#define POST_SOC_SPECIFIC_8 0x58 +#define POST_SOC_SPECIFIC_9 0x59 +#define POST_SOC_SPECIFIC_10 0x5a +#define POST_SOC_SPECIFIC_11 0x5b +#define POST_SOC_SPECIFIC_12 0x5c +#define POST_SOC_SPECIFIC_13 0x5d +#define POST_SOC_SPECIFIC_14 0x5e +#define POST_SOC_SPECIFIC_15 0x5f + +/** * \brief Before enabling the cache * * Going to enable the cache