Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46312 )
Change subject: soc/intel/common: Move CSE RW into new FMAP region to optimize boot time
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Patch Set 7:
Patch Set 5:
Patch Set 5:
We still need to evaluate the downstream effects of this change on the rest of our infrastructure, tooling, etc. That's not to say we won't go this route, but we need to be a little more thorough with making sure all of our ebuilds, other tools, etc. that rely on the current flash layout to make sure they are up to date with this as well.
+1 to what Tim said. There are a number of factors that will have to be evaluated to ensure that we do not silently break or cause incompatibilities with any of the existing infrastructure:
- Signer
- Futility
- Firmware updater (both RO+RW as well as RW only)
- Autotest lab firmware recovery
- FAFT
...
Sridhar/Rizwan - have you evaluated the impact of the change on rest of the infrastructure? Is this captured anywhere?
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