Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33430 )
Change subject: grunt: Change Bayhub eMMC base clock to 200MHz ......................................................................
grunt: Change Bayhub eMMC base clock to 200MHz
The clock was previously set to 52MHz to workaround the fact that depthcharge didn't support tuning.
Tuning has now been enabled in depthcharge: https://chromium-review.googlesource.com/c/chromiumos/platform/depthcharge/+...
BUG=b:122244718 TEST=Verified on grunt that it speeds up boot by 130ms
Change-Id: If847cea2a7848bcd175958db86e652d4f710201a Signed-off-by: Raul E Rangel rrangel@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/33430 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Martin Roth martinroth@google.com --- M src/mainboard/google/kahlee/variants/baseboard/mainboard.c 1 file changed, 12 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved
diff --git a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c index 996e610..95274eb 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c +++ b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c @@ -61,12 +61,22 @@ write32((void *)(sdbar + BH720_MEM_RW_ADR), BH720_MEM_RW_WRITE | BH720_PCR_EMMC_SETTING);
- /* Set Bayhub SD base CLK 50MHz: case#1 PCR 0x3E4[22] = 0 */ + /* Set Base clock to 200MHz(PCR 0x304[31:16] = 0x2510) */ + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_READ | BH720_PCR_DrvStrength_PLL); + bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); + bh720_pcr_data &= 0x0000FFFF; + bh720_pcr_data |= 0x2510 << 16; + write32((void *)(sdbar + BH720_MEM_RW_DATA), bh720_pcr_data); + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_WRITE | BH720_PCR_DrvStrength_PLL); + + /* Use PLL Base clock PCR 0x3E4[22] = 1 */ write32((void *)(sdbar + BH720_MEM_RW_ADR), BH720_MEM_RW_READ | BH720_PCR_CSR); bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); write32((void *)(sdbar + BH720_MEM_RW_DATA), - bh720_pcr_data & ~BH720_PCR_CSR_EMMC_MODE_SEL); + bh720_pcr_data | BH720_PCR_CSR_EMMC_MODE_SEL); write32((void *)(sdbar + BH720_MEM_RW_ADR), BH720_MEM_RW_WRITE | BH720_PCR_CSR);