[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Update DCACHE_BSP_STACK_SIZE

[9elements QA (Code Review)]

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39706 )

Change subject: soc/intel/tigerlake: Update DCACHE_BSP_STACK_SIZE
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Patch Set 3:

Automatic boot test returned (PASS/FAIL/TOTAL): 5/0/5
Emulation targets:
EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/1646
EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1645
EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1644
Non-emulation targets:
HP_COMPAQ_8200_ELITE_SFF_PC using payload TianoCore : SUCCESS : https://lava.9esec.io/r/1648
HP_COMPAQ_8200_ELITE_SFF_PC using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1647

Please note: This test is under development and might not be accurate at all!