Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29684
Change subject: soc/intel/common: Bring DISPLAY_MTRRS into the light ......................................................................
soc/intel/common: Bring DISPLAY_MTRRS into the light
Initially, I wanted to move only the Kconfig DISPLAY_MTRRS into the "Debug" menu. It turned out, though, that the code looks rather generic and while it's not perfect, I see nothing to be ashamed of. No need to hide it in soc/intel/.
If somebody wants to review the code if it's 100% generic, we could even get rid of HAVE_DISPLAY_MTRRS.
Change-Id: Ibd0a64121bd6e4ab5d7fd835f3ac25d3f5011f24 Signed-off-by: Nico Huber nico.h@gmx.de --- M Documentation/Intel/Board/Galileo_checklist.html M Documentation/Intel/SoC/soc.html M src/Kconfig M src/arch/x86/postcar.c M src/cpu/x86/mtrr/Makefile.inc A src/cpu/x86/mtrr/debug.c M src/cpu/x86/mtrr/earlymtrr.c M src/drivers/intel/fsp1_1/after_raminit.S M src/drivers/intel/fsp1_1/car.c M src/drivers/intel/fsp1_1/include/fsp/ramstage.h M src/drivers/intel/fsp1_1/include/fsp/romstage.h M src/drivers/intel/fsp1_1/stack.c M src/drivers/intel/fsp2_0/debug.c M src/drivers/intel/fsp2_0/notify.c M src/include/cpu/x86/mtrr.h M src/soc/intel/common/Kconfig M src/soc/intel/common/Makefile.inc D src/soc/intel/common/util.c D src/soc/intel/common/util.h M src/soc/intel/quark/Makefile.inc M src/soc/intel/quark/bootblock/bootblock.c M src/soc/intel/quark/include/soc/ramstage.h M src/soc/intel/quark/romstage/mtrr.c M src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat M src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat M src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat M src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat 27 files changed, 247 insertions(+), 313 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/29684/1
diff --git a/Documentation/Intel/Board/Galileo_checklist.html b/Documentation/Intel/Board/Galileo_checklist.html index 3fc04b1..397f570 100644 --- a/Documentation/Intel/Board/Galileo_checklist.html +++ b/Documentation/Intel/Board/Galileo_checklist.html @@ -79,8 +79,6 @@ <tr bgcolor=#ffc0c0><td>Required</td><td>smm_region_size</td></tr> <tr bgcolor=#c0ffc0><td>Required</td><td>soc_after_ram_init</td></tr> <tr bgcolor=#c0ffc0><td>Required</td><td>soc_display_memory_init_params</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>soc_display_mtrrs</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>soc_get_variable_mtrr_count</td></tr> <tr bgcolor=#c0ffc0><td>Required</td><td>soc_memory_init_params</td></tr> <tr bgcolor=#ffffc0><td>Optional</td><td>soc_pre_ram_init</td></tr> <tr bgcolor=#ffffc0><td>Optional</td><td>southbridge_smi_handler</td></tr> diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html index 29b819e..fff536b 100644 --- a/Documentation/Intel/SoC/soc.html +++ b/Documentation/Intel/SoC/soc.html @@ -234,8 +234,6 @@ <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc">src/drivers/intel/fsp1_1/cache_as_ram.inc</a> </li> <li>Add "select SOC_INTEL_COMMON" to enable the use of the files from src/soc/intel/common - specifically building - <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/soc/intel/common/util.c">util.c</a> </li> </ol> </li> diff --git a/src/Kconfig b/src/Kconfig index ce584f5..b14fa32 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -700,6 +700,13 @@ bool "Output verbose GPIO debug messages" depends on HAVE_DEBUG_GPIO
+config HAVE_DISPLAY_MTRRS + bool + +config DISPLAY_MTRRS + bool "Display intermediate MTRR settings" + depends on HAVE_DISPLAY_MTRRS + config DEBUG_CBFS bool "Output verbose CBFS debug messages" default n diff --git a/src/arch/x86/postcar.c b/src/arch/x86/postcar.c index 295276b..ea05824 100644 --- a/src/arch/x86/postcar.c +++ b/src/arch/x86/postcar.c @@ -16,9 +16,9 @@ #include <arch/cpu.h> #include <cbmem.h> #include <console/console.h> +#include <cpu/x86/mtrr.h> #include <main_decl.h> #include <program_loading.h> -#include <soc/intel/common/util.h>
/* * Systems without a native coreboot cache-as-ram teardown may implement @@ -35,9 +35,7 @@ /* Recover cbmem so infrastruture using it is functional. */ cbmem_initialize();
- /* Display the MTRRs */ - if (IS_ENABLED(CONFIG_DISPLAY_MTRRS)) - soc_display_mtrrs(); + display_mtrrs();
/* Load and run ramstage. */ run_ramstage(); diff --git a/src/cpu/x86/mtrr/Makefile.inc b/src/cpu/x86/mtrr/Makefile.inc index e6e9c50..caa6e9c 100644 --- a/src/cpu/x86/mtrr/Makefile.inc +++ b/src/cpu/x86/mtrr/Makefile.inc @@ -1,3 +1,9 @@ -ramstage-y += mtrr.c -romstage-y += earlymtrr.c -bootblock-y += earlymtrr.c +ramstage-y += mtrr.c + +romstage-y += earlymtrr.c +bootblock-y += earlymtrr.c + +bootblock-y += debug.c +romstage-y += debug.c +postcar-y += debug.c +ramstage-y += debug.c diff --git a/src/cpu/x86/mtrr/debug.c b/src/cpu/x86/mtrr/debug.c new file mode 100644 index 0000000..c562d84 --- /dev/null +++ b/src/cpu/x86/mtrr/debug.c @@ -0,0 +1,202 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <cpu/cpu.h> +#include <cpu/x86/mtrr.h> +#include <stdint.h> + +static const char *display_mtrr_type(uint32_t type) +{ + switch (type) { + default: return "reserved"; + case 0: return "UC"; + case 1: return "WC"; + case 4: return "WT"; + case 5: return "WP"; + case 6: return "WB"; + case 7: return "UC-"; + } +} + +static void display_mtrr_fixed_types(uint64_t msr, + uint32_t starting_address, uint32_t memory_size) +{ + uint32_t base_address; + uint32_t index; + uint32_t next_address; + uint32_t next_type; + uint32_t type; + + type = msr & MTRR_DEF_TYPE_MASK; + base_address = starting_address; + next_address = base_address; + for (index = 0; index < 64; index += 8) { + next_address = starting_address + (memory_size * + ((index >> 3) + 1)); + next_type = (msr >> index) & MTRR_DEF_TYPE_MASK; + if (next_type != type) { + printk(BIOS_DEBUG, " 0x%08x - 0x%08x: %s\n", + base_address, next_address - 1, + display_mtrr_type(type)); + base_address = next_address; + type = next_type; + } + } + if (base_address != next_address) + printk(BIOS_DEBUG, " 0x%08x - 0x%08x: %s\n", + base_address, next_address - 1, + display_mtrr_type(type)); +} + +static void display_4k_mtrr(uint32_t msr_reg, uint32_t starting_address, + const char *name) +{ + union { + uint64_t u64; + msr_t s; + } msr; + + msr.s = rdmsr(msr_reg); + printk(BIOS_DEBUG, "0x%016llx: %s\n", msr.u64, name); + display_mtrr_fixed_types(msr.u64, starting_address, 0x1000); +} + +static void display_16k_mtrr(uint32_t msr_reg, uint32_t starting_address, + const char *name) +{ + union { + uint64_t u64; + msr_t s; + } msr; + + msr.s = rdmsr(msr_reg); + printk(BIOS_DEBUG, "0x%016llx: %s\n", msr.u64, name); + display_mtrr_fixed_types(msr.u64, starting_address, 0x4000); +} + +static void display_64k_mtrr(void) +{ + union { + uint64_t u64; + msr_t s; + } msr; + + msr.s = rdmsr(MTRR_FIX_64K_00000); + printk(BIOS_DEBUG, "0x%016llx: IA32_MTRR_FIX64K_00000\n", msr.u64); + display_mtrr_fixed_types(msr.u64, 0, 0x10000); +} + +static void display_mtrrcap(void) +{ + msr_t msr; + + msr = rdmsr(MTRR_CAP_MSR); + printk(BIOS_DEBUG, + "0x%08x%08x: IA32_MTRRCAP: %s%s%s%u variable MTRRs\n", + msr.hi, msr.lo, + (msr.lo & MTRR_CAP_SMRR) ? "SMRR, " : "", + (msr.lo & MTRR_CAP_WC) ? "WC, " : "", + (msr.lo & MTRR_CAP_FIX) ? "FIX, " : "", + msr.lo & MTRR_CAP_VCNT); +} + +static void display_mtrr_def_type(void) +{ + union { + uint64_t u64; + msr_t s; + } msr; + + msr.s = rdmsr(MTRR_DEF_TYPE_MSR); + printk(BIOS_DEBUG, "0x%016llx: IA32_MTRR_DEF_TYPE:%s%s %s\n", + msr.u64, + (msr.u64 & MTRR_DEF_TYPE_EN) ? " E," : "", + (msr.u64 & MTRR_DEF_TYPE_FIX_EN) ? " FE," : "", + display_mtrr_type((uint32_t)(msr.u64 & + MTRR_DEF_TYPE_MASK))); +} + +static void display_variable_mtrr(int index, uint64_t address_mask) +{ + const uint32_t msr_reg = MTRR_PHYS_BASE(index); + uint64_t base_address; + uint64_t length; + uint64_t mask; + union { + uint64_t u64; + msr_t s; + } msr_a; + union { + uint64_t u64; + msr_t s; + } msr_m; + + msr_a.s = rdmsr(msr_reg); + msr_m.s = rdmsr(msr_reg + 1); + if (msr_m.u64 & MTRR_PHYS_MASK_VALID) { + base_address = (msr_a.u64 & 0xfffffffffffff000ULL) + & address_mask; + printk(BIOS_DEBUG, + "0x%016llx: PHYBASE%d: Address = 0x%016llx, %s\n", + msr_a.u64, index, base_address, + display_mtrr_type(msr_a.u64 & MTRR_DEF_TYPE_MASK)); + mask = (msr_m.u64 & 0xfffffffffffff000ULL) & address_mask; + length = (~mask & address_mask) + 1; + printk(BIOS_DEBUG, + "0x%016llx: PHYMASK%d: Length = 0x%016llx, Valid\n", + msr_m.u64, index, length); + } else { + printk(BIOS_DEBUG, "0x%016llx: PHYBASE%d\n", msr_a.u64, index); + printk(BIOS_DEBUG, "0x%016llx: PHYMASK%d: Disabled\n", + msr_m.u64, index); + } +} + +static void _display_mtrrs(void) +{ + uint32_t address_bits; + uint64_t address_mask; + int i; + int variable_mtrrs; + + /* Display the fixed MTRRs */ + display_mtrrcap(); + display_mtrr_def_type(); + display_64k_mtrr(); + display_16k_mtrr(MTRR_FIX_16K_80000, 0x80000, "IA32_MTRR_FIX16K_80000"); + display_16k_mtrr(MTRR_FIX_16K_A0000, 0xa0000, "IA32_MTRR_FIX16K_A0000"); + display_4k_mtrr(MTRR_FIX_4K_C0000, 0xc0000, "IA32_MTRR_FIX4K_C0000"); + display_4k_mtrr(MTRR_FIX_4K_C8000, 0xc8000, "IA32_MTRR_FIX4K_C8000"); + display_4k_mtrr(MTRR_FIX_4K_D0000, 0xd0000, "IA32_MTRR_FIX4K_D0000"); + display_4k_mtrr(MTRR_FIX_4K_D8000, 0xd8000, "IA32_MTRR_FIX4K_D8000"); + display_4k_mtrr(MTRR_FIX_4K_E0000, 0xe0000, "IA32_MTRR_FIX4K_E0000"); + display_4k_mtrr(MTRR_FIX_4K_E8000, 0xe8000, "IA32_MTRR_FIX4K_E8000"); + display_4k_mtrr(MTRR_FIX_4K_F0000, 0xf0000, "IA32_MTRR_FIX4K_F0000"); + display_4k_mtrr(MTRR_FIX_4K_F8000, 0xf8000, "IA32_MTRR_FIX4K_F8000"); + address_bits = cpu_phys_address_size(); + address_mask = (1ULL << address_bits) - 1; + + /* Display the variable MTRRs */ + variable_mtrrs = get_var_mtrr_count(); + for (i = 0; i < variable_mtrrs; i++) + display_variable_mtrr(i, address_mask); +} + +asmlinkage void display_mtrrs(void) +{ + if (IS_ENABLED(CONFIG_DISPLAY_MTRRS)) + _display_mtrrs(); +} diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index 4ee54a3..02ad85f 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -20,13 +20,11 @@ */ int get_free_var_mtrr(void) { - msr_t msr, maskm; + msr_t maskm; int vcnt; int i;
- /* Read MTRRCap and get vcnt - variable memory type ranges. */ - msr = rdmsr(MTRR_CAP_MSR); - vcnt = msr.lo & 0xff; + vcnt = get_var_mtrr_count();
/* Identify the first var mtrr which is not valid. */ for (i = 0; i < vcnt; i++) { diff --git a/src/drivers/intel/fsp1_1/after_raminit.S b/src/drivers/intel/fsp1_1/after_raminit.S index cd56ea8..cdc8e93 100644 --- a/src/drivers/intel/fsp1_1/after_raminit.S +++ b/src/drivers/intel/fsp1_1/after_raminit.S @@ -66,7 +66,7 @@ 1: #endif /* Display the MTRRs */ - call soc_display_mtrrs + call display_mtrrs
/* * The stack contents are initialized in src/soc/intel/common/stack.c diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 4016ba1..13161d6 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -15,10 +15,10 @@
#include <arch/early_variables.h> #include <console/console.h> +#include <cpu/x86/mtrr.h> #include <fsp/car.h> #include <fsp/util.h> #include <program_loading.h> -#include <soc/intel/common/util.h> #include <timestamp.h>
FSP_INFO_HEADER *fih_car CAR_GLOBAL; @@ -95,7 +95,7 @@ { timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_END); printk(BIOS_DEBUG, "FspTempRamExit returned successfully\n"); - soc_display_mtrrs(); + display_mtrrs();
after_cache_as_ram_stage(); } diff --git a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h index a9f6a8d..13769b3 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h @@ -18,7 +18,6 @@ #define _INTEL_COMMON_RAMSTAGE_H_
#include <fsp/util.h> -#include <soc/intel/common/util.h> #include <stdint.h>
/* diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h index d79be70..e266bee 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h @@ -22,7 +22,6 @@ #include <memory_info.h> #include <fsp/car.h> #include <fsp/util.h> -#include <soc/intel/common/util.h> #include <soc/intel/common/mma.h> #include <soc/pei_wrapper.h> #include <soc/pm.h> /* chip_power_state */ diff --git a/src/drivers/intel/fsp1_1/stack.c b/src/drivers/intel/fsp1_1/stack.c index 06c0e63..eb2a637 100644 --- a/src/drivers/intel/fsp1_1/stack.c +++ b/src/drivers/intel/fsp1_1/stack.c @@ -38,12 +38,12 @@ uint32_t *slot;
/* Display the MTRRs */ - soc_display_mtrrs(); + display_mtrrs();
/* Top of stack needs to be aligned to a 8-byte boundary. */ slot = (void *)romstage_ram_stack_top(); num_mtrrs = 0; - max_mtrrs = soc_get_variable_mtrr_count(NULL); + max_mtrrs = get_var_mtrr_count();
/* * The upper bits of the MTRR mask need to set according to the number diff --git a/src/drivers/intel/fsp2_0/debug.c b/src/drivers/intel/fsp2_0/debug.c index 8f4dc1e..d098772 100644 --- a/src/drivers/intel/fsp2_0/debug.c +++ b/src/drivers/intel/fsp2_0/debug.c @@ -11,8 +11,8 @@
#include <console/console.h> #include <console/streams.h> +#include <cpu/x86/mtrr.h> #include <fsp/util.h> -#include <soc/intel/common/util.h>
asmlinkage size_t fsp_write_line(uint8_t *buffer, size_t number_of_bytes) { @@ -28,9 +28,7 @@ const FSPM_UPD *fspm_old_upd, const FSPM_UPD *fspm_new_upd) { - /* Display the MTRRs */ - if (IS_ENABLED(CONFIG_DISPLAY_MTRRS)) - soc_display_mtrrs(); + display_mtrrs();
/* Display the UPD values */ if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA)) @@ -62,9 +60,7 @@ if (IS_ENABLED(CONFIG_VERIFY_HOBS)) fsp_verify_memory_init_hobs();
- /* Display the MTRRs */ - if (IS_ENABLED(CONFIG_DISPLAY_MTRRS)) - soc_display_mtrrs(); + display_mtrrs(); }
/*----------- @@ -75,9 +71,7 @@ const FSPS_UPD *fsps_old_upd, const FSPS_UPD *fsps_new_upd) { - /* Display the MTRRs */ - if (IS_ENABLED(CONFIG_DISPLAY_MTRRS)) - soc_display_mtrrs(); + display_mtrrs();
/* Display the UPD values */ if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA)) @@ -99,9 +93,7 @@ if (IS_ENABLED(CONFIG_DISPLAY_HOBS)) fsp_display_hobs();
- /* Display the MTRRs */ - if (IS_ENABLED(CONFIG_DISPLAY_MTRRS)) - soc_display_mtrrs(); + display_mtrrs(); }
/*----------- @@ -129,7 +121,5 @@ if (IS_ENABLED(CONFIG_DISPLAY_HOBS)) fsp_display_hobs();
- /* Display the MTRRs */ - if (IS_ENABLED(CONFIG_DISPLAY_MTRRS)) - soc_display_mtrrs(); + display_mtrrs(); } diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c index c3a2804..a5c7ef0 100644 --- a/src/drivers/intel/fsp2_0/notify.c +++ b/src/drivers/intel/fsp2_0/notify.c @@ -12,8 +12,8 @@
#include <bootstate.h> #include <console/console.h> +#include <cpu/x86/mtrr.h> #include <fsp/util.h> -#include <soc/intel/common/util.h> #include <string.h> #include <timestamp.h>
@@ -70,9 +70,7 @@ { enum fsp_notify_phase phase = (uint32_t)arg;
- /* Display the MTRRs */ - if (IS_ENABLED(CONFIG_DISPLAY_MTRRS)) - soc_display_mtrrs(); + display_mtrrs();
fsp_notify(phase); if (phase == READY_TO_BOOT) diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 1f704ac..eb7d78d 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -99,10 +99,17 @@ * This function needs to be called after the first MTRR solution is derived. */ void mtrr_use_temp_range(uintptr_t begin, size_t size, int type);
+static inline int get_var_mtrr_count(void) +{ + return rdmsr(MTRR_CAP_MSR).lo & MTRR_CAP_VCNT; +} + void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size, unsigned int type); int get_free_var_mtrr(void);
+asmlinkage void display_mtrrs(void); + /* * Set the MTRRs using the data on the stack from setup_stack_and_mtrrs. * Return a new top_of_stack value which removes the setup_stack_and_mtrrs data. diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 27d3f59..b5caf40 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -1,5 +1,6 @@ config SOC_INTEL_COMMON bool + select HAVE_DISPLAY_MTRRS help common code for Intel SOCs
@@ -14,10 +15,6 @@ comment "Intel SoC Common coreboot stages" source "src/soc/intel/common/basecode/Kconfig"
-config DISPLAY_MTRRS - bool "MTRRs: Display the MTRR settings" - default n - config DISPLAY_SMM_MEMORY_MAP bool "SMM: Display the SMM memory map" default n diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 11a4575..22d350c 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -4,23 +4,18 @@ subdirs-y += block/ subdirs-y += pch/
-bootblock-y += util.c - verstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
bootblock-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c -romstage-y += util.c romstage-$(CONFIG_MMA) += mma.c romstage-y += smbios.c
-postcar-y += util.c postcar-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
ramstage-y += hda_verb.c ramstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c -ramstage-y += util.c ramstage-$(CONFIG_MMA) += mma.c ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c ramstage-y += vbt.c diff --git a/src/soc/intel/common/util.c b/src/soc/intel/common/util.c deleted file mode 100644 index fadef60..0000000 --- a/src/soc/intel/common/util.c +++ /dev/null @@ -1,224 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015-2016 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <cpu/cpu.h> -#include <cpu/x86/mtrr.h> -#include <soc/intel/common/util.h> -#include <stddef.h> - -uint32_t soc_get_variable_mtrr_count(uint64_t *msr) -{ - union { - uint64_t u64; - msr_t s; - } mtrrcap; - - mtrrcap.s = rdmsr(MTRR_CAP_MSR); - if (msr != NULL) - *msr = mtrrcap.u64; - return mtrrcap.u64 & MTRR_CAP_VCNT; -} - -static const char *soc_display_mtrr_type(uint32_t type) -{ - switch (type) { - default: return "reserved"; - case 0: return "UC"; - case 1: return "WC"; - case 4: return "WT"; - case 5: return "WP"; - case 6: return "WB"; - case 7: return "UC-"; - } -} - -static void soc_display_mtrr_fixed_types(uint64_t msr, - uint32_t starting_address, uint32_t memory_size) -{ - uint32_t base_address; - uint32_t index; - uint32_t next_address; - uint32_t next_type; - uint32_t type; - - type = msr & MTRR_DEF_TYPE_MASK; - base_address = starting_address; - next_address = base_address; - for (index = 0; index < 64; index += 8) { - next_address = starting_address + (memory_size * - ((index >> 3) + 1)); - next_type = (msr >> index) & MTRR_DEF_TYPE_MASK; - if (next_type != type) { - printk(BIOS_DEBUG, " 0x%08x - 0x%08x: %s\n", - base_address, next_address - 1, - soc_display_mtrr_type(type)); - base_address = next_address; - type = next_type; - } - } - if (base_address != next_address) - printk(BIOS_DEBUG, " 0x%08x - 0x%08x: %s\n", - base_address, next_address - 1, - soc_display_mtrr_type(type)); -} - -static void soc_display_4k_mtrr(uint32_t msr_reg, uint32_t starting_address, - const char *name) -{ - union { - uint64_t u64; - msr_t s; - } msr; - - msr.s = rdmsr(msr_reg); - printk(BIOS_DEBUG, "0x%016llx: %s\n", msr.u64, name); - soc_display_mtrr_fixed_types(msr.u64, starting_address, 0x1000); -} - -static void soc_display_16k_mtrr(uint32_t msr_reg, uint32_t starting_address, - const char *name) -{ - union { - uint64_t u64; - msr_t s; - } msr; - - msr.s = rdmsr(msr_reg); - printk(BIOS_DEBUG, "0x%016llx: %s\n", msr.u64, name); - soc_display_mtrr_fixed_types(msr.u64, starting_address, 0x4000); -} - -static void soc_display_64k_mtrr(void) -{ - union { - uint64_t u64; - msr_t s; - } msr; - - msr.s = rdmsr(MTRR_FIX_64K_00000); - printk(BIOS_DEBUG, "0x%016llx: IA32_MTRR_FIX64K_00000\n", msr.u64); - soc_display_mtrr_fixed_types(msr.u64, 0, 0x10000); -} - -static uint32_t soc_display_mtrrcap(void) -{ - uint64_t msr; - uint32_t variable_mtrrs; - - variable_mtrrs = soc_get_variable_mtrr_count(&msr); - printk(BIOS_DEBUG, - "0x%016llx: IA32_MTRRCAP: %s%s%s%d variable MTRRs\n", - msr, - (msr & MTRR_CAP_SMRR) ? "SMRR, " : "", - (msr & MTRR_CAP_WC) ? "WC, " : "", - (msr & MTRR_CAP_FIX) ? "FIX, " : "", - variable_mtrrs); - return variable_mtrrs; -} - -static void soc_display_mtrr_def_type(void) -{ - union { - uint64_t u64; - msr_t s; - } msr; - - msr.s = rdmsr(MTRR_DEF_TYPE_MSR); - printk(BIOS_DEBUG, "0x%016llx: IA32_MTRR_DEF_TYPE:%s%s %s\n", - msr.u64, - (msr.u64 & MTRR_DEF_TYPE_EN) ? " E," : "", - (msr.u64 & MTRR_DEF_TYPE_FIX_EN) ? " FE," : "", - soc_display_mtrr_type((uint32_t)(msr.u64 & - MTRR_DEF_TYPE_MASK))); -} - -static void soc_display_variable_mtrr(uint32_t msr_reg, int index, - uint64_t address_mask) -{ - uint64_t base_address; - uint64_t length; - uint64_t mask; - union { - uint64_t u64; - msr_t s; - } msr_a; - union { - uint64_t u64; - msr_t s; - } msr_m; - - msr_a.s = rdmsr(msr_reg); - msr_m.s = rdmsr(msr_reg + 1); - if (msr_m.u64 & MTRR_PHYS_MASK_VALID) { - base_address = (msr_a.u64 & 0xfffffffffffff000ULL) - & address_mask; - printk(BIOS_DEBUG, - "0x%016llx: PHYBASE%d: Address = 0x%016llx, %s\n", - msr_a.u64, index, base_address, - soc_display_mtrr_type(msr_a.u64 & MTRR_DEF_TYPE_MASK)); - mask = (msr_m.u64 & 0xfffffffffffff000ULL) & address_mask; - length = (~mask & address_mask) + 1; - printk(BIOS_DEBUG, - "0x%016llx: PHYMASK%d: Length = 0x%016llx, Valid\n", - msr_m.u64, index, length); - } else { - printk(BIOS_DEBUG, "0x%016llx: PHYBASE%d\n", msr_a.u64, index); - printk(BIOS_DEBUG, "0x%016llx: PHYMASK%d: Disabled\n", - msr_m.u64, index); - } -} - -asmlinkage void soc_display_mtrrs(void) -{ - if (IS_ENABLED(CONFIG_DISPLAY_MTRRS)) { - uint32_t address_bits; - uint64_t address_mask; - int i; - int variable_mtrrs; - - /* Display the fixed MTRRs */ - variable_mtrrs = soc_display_mtrrcap(); - soc_display_mtrr_def_type(); - soc_display_64k_mtrr(); - soc_display_16k_mtrr(MTRR_FIX_16K_80000, 0x80000, - "IA32_MTRR_FIX16K_80000"); - soc_display_16k_mtrr(MTRR_FIX_16K_A0000, 0xa0000, - "IA32_MTRR_FIX16K_A0000"); - soc_display_4k_mtrr(MTRR_FIX_4K_C0000, 0xc0000, - "IA32_MTRR_FIX4K_C0000"); - soc_display_4k_mtrr(MTRR_FIX_4K_C8000, 0xc8000, - "IA32_MTRR_FIX4K_C8000"); - soc_display_4k_mtrr(MTRR_FIX_4K_D0000, 0xd0000, - "IA32_MTRR_FIX4K_D0000"); - soc_display_4k_mtrr(MTRR_FIX_4K_D8000, 0xd8000, - "IA32_MTRR_FIX4K_D8000"); - soc_display_4k_mtrr(MTRR_FIX_4K_E0000, 0xe0000, - "IA32_MTRR_FIX4K_E0000"); - soc_display_4k_mtrr(MTRR_FIX_4K_E8000, 0xe8000, - "IA32_MTRR_FIX4K_E8000"); - soc_display_4k_mtrr(MTRR_FIX_4K_F0000, 0xf0000, - "IA32_MTRR_FIX4K_F0000"); - soc_display_4k_mtrr(MTRR_FIX_4K_F8000, 0xf8000, - "IA32_MTRR_FIX4K_F8000"); - address_bits = cpu_phys_address_size(); - address_mask = (1ULL << address_bits) - 1; - - /* Display the variable MTRRs */ - for (i = 0; i < variable_mtrrs; i++) - soc_display_variable_mtrr(MTRR_PHYS_BASE(i), i, - address_mask); - } -} diff --git a/src/soc/intel/common/util.h b/src/soc/intel/common/util.h deleted file mode 100644 index 854f2b0..0000000 --- a/src/soc/intel/common/util.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _INTEL_COMMON_UTIL_H_ -#define _INTEL_COMMON_UTIL_H_ - -#include <arch/cpu.h> -#include <cpu/x86/msr.h> -#include <stdint.h> - -asmlinkage void soc_display_mtrrs(void); -uint32_t soc_get_variable_mtrr_count(uint64_t *msr); - -#endif /* _INTEL_COMMON_UTIL_H_ */ diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index 741f5d3..654f0a7 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -16,6 +16,7 @@ ifeq ($(CONFIG_SOC_INTEL_QUARK),y)
subdirs-y += romstage +subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/tsc
bootblock-y += bootblock/esram_init.S diff --git a/src/soc/intel/quark/bootblock/bootblock.c b/src/soc/intel/quark/bootblock/bootblock.c index 38730ea..d3aa900 100644 --- a/src/soc/intel/quark/bootblock/bootblock.c +++ b/src/soc/intel/quark/bootblock/bootblock.c @@ -15,10 +15,10 @@ */ #include <bootblock_common.h> #include <console/console.h> +#include <cpu/x86/mtrr.h> #include <device/pci_def.h> #include <program_loading.h> #include <soc/iomap.h> -#include <soc/intel/common/util.h> #include <soc/pci_devs.h> #include <soc/reg_access.h>
@@ -112,8 +112,7 @@ if (IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_SOC_INIT_ENTRY)) light_sd_led();
- /* Display the MTRRs */ - soc_display_mtrrs(); + display_mtrrs(); }
void platform_prog_run(struct prog *prog) diff --git a/src/soc/intel/quark/include/soc/ramstage.h b/src/soc/intel/quark/include/soc/ramstage.h index 4ad0fedc..821f43e 100644 --- a/src/soc/intel/quark/include/soc/ramstage.h +++ b/src/soc/intel/quark/include/soc/ramstage.h @@ -17,6 +17,7 @@ #ifndef _SOC_RAMSTAGE_H_ #define _SOC_RAMSTAGE_H_
+#include <arch/cpu.h> #include <chip.h> #include <device/device.h> #if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) diff --git a/src/soc/intel/quark/romstage/mtrr.c b/src/soc/intel/quark/romstage/mtrr.c index 6f2f00c..47bfde4 100644 --- a/src/soc/intel/quark/romstage/mtrr.c +++ b/src/soc/intel/quark/romstage/mtrr.c @@ -16,7 +16,6 @@
#include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> -#include <soc/intel/common/util.h> #include <soc/pci_devs.h> #include <soc/reg_access.h>
diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat index 267673a..3417212 100644 --- a/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat @@ -40,8 +40,6 @@ smm_region_size soc_after_ram_init soc_display_memory_init_params -soc_display_mtrrs -soc_get_variable_mtrr_count soc_memory_init_params soc_pre_ram_init southbridge_smi_handler diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat index 70f204d..0835190 100644 --- a/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat @@ -23,8 +23,6 @@ save_chromeos_gpios soc_after_ram_init soc_display_memory_init_params -soc_display_mtrrs -soc_get_variable_mtrr_count soc_memory_init_params soc_pre_ram_init southbridge_smi_handler diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat index 2124f0f..0910152 100644 --- a/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat @@ -22,8 +22,6 @@ platform_prog_run platform_segment_loaded save_chromeos_gpios -soc_display_mtrrs -soc_get_variable_mtrr_count stage_cache_add stage_cache_load_stage timestamp_get diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat index f589eaa..fe1f0d9 100644 --- a/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat @@ -9,8 +9,6 @@ mainboard_post platform_prog_run platform_segment_loaded -soc_display_mtrrs -soc_get_variable_mtrr_count stage_cache_add stage_cache_load_stage timestamp_get