Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32651 )
Change subject: soc/amd/stoneyridge: Move GPIO support to common ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/#/c/32651/2/src/mainboard/google/kahlee/mainboar... File src/mainboard/google/kahlee/mainboard.c:
https://review.coreboot.org/#/c/32651/2/src/mainboard/google/kahlee/mainboar... PS2, Line 30: <soc/smi.h> :
Why is smi. […]
Looks like that's left over from crud I used to have in here, but seems to build OK w/o the addition. I'll remove.
https://review.coreboot.org/#/c/32651/2/src/soc/amd/stoneyridge/include/soc/... File src/soc/amd/stoneyridge/include/soc/gpio.h:
https://review.coreboot.org/#/c/32651/2/src/soc/amd/stoneyridge/include/soc/... PS2, Line 75:
Could you leave GPIO_BANK0_CONTROL, GPIO_BANK1_CONTROL and GPI2_BANK0_CONTROL in gpio. […]
It won't have a different MMIO offset as the MMIO offsets have remained consistent over the last 10 years. There are two implementations of GPIOs The older one squeezed everything into the block at +100. The newer deprecated the use of +100 and implements 3 banks at +1500/1600/1700. Every device that falls within each of the two categories behaves like all the others in that category. This is also why I chose to name the newer feature "SOC_AMD_COMMON_BLOCK_BANKED_GPIOS". In the event we ever implemented the older one here, it wouldn't be banked.