[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Correct TCSS XHCI Port status offset

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Maulik V Vaghela, Sridhar Siricilla, Subrata Banik, Balaji Manigandan, Deepti Deshatty, Patrick Rudolph.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55230 )

Change subject: soc/intel/alderlake: Correct TCSS XHCI Port status offset
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Patch Set 2:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/55230/comment/bc95b28a_280db63a 
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