[coreboot-gerrit] Change in coreboot[master]: soc/intel/common: Add ASL for TCSS PCI segment

[Subrata Banik (Code Review)]

Hello build bot (Jenkins), Patrick Georgi, Patrick Rudolph, HAOUAS Elyes,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/41011

to look at the new patch set (#3).

Change subject: soc/intel/common: Add ASL for TCSS PCI segment
......................................................................

soc/intel/common: Add ASL for TCSS PCI segment

Refer from Intel RC:
https://github.com/otcshare/CCG-TGL-Generic-SiC/tree/master/ClientOneSilicon...

PCI1 device been created based on TCSS_PCIE_SEGMENT selection
from MB Kconfig

extracted build/dsdt.aml

Device (PCI1)
{
    Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */)  // _HID: Hardware ID
    Name (_CID, EisaId ("PNP0A03") /* PCI Bus */)  // _CID: Compatible ID
    Name (_SEG, One)  // _SEG: PCI Segment
    Name (_UID, One)  // _UID: Unique ID
....
}

Change-Id: I43924a3a34173ba3531079ef848f1935c59bb74a
Signed-off-by: Subrata Banik 
---
A src/soc/intel/common/block/acpi/acpi/extrahostbridge.asl
A src/soc/intel/common/block/acpi/acpi/pcisegment.asl
2 files changed, 127 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/41011/3