[coreboot-gerrit] Change in coreboot[master]: vendercode/intel/fsp/fsp2_0/glk: Update FSP header file per v2.2.0

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44435 )

Change subject: vendercode/intel/fsp/fsp2_0/glk: Update FSP header file per v2.2.0
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vendercode/intel/fsp/fsp2_0/glk: Update FSP header file per v2.2.0

Update FSP header file to match GLK FSP v2.2.0

BUG=none
BRANCH=none
TEST=none

Change-Id: I515b4c44439e3404d3b06d587f0846457000fdb4
Signed-off-by: Seunghwan Kim 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44435
Tested-by: build bot (Jenkins) 
Reviewed-by: Marx Wang 
Reviewed-by: Tim Wawrzynczak 
Reviewed-by: Furquan Shaikh 
Reviewed-by: Karthik Ramasubramanian 
---
M src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h
1 file changed, 15 insertions(+), 15 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Marx Wang: Looks good to me, but someone else must approve
  Karthik Ramasubramanian: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h
index 97a40b6..0d3902d 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h
@@ -1715,33 +1715,33 @@
 **/
   UINT8                       SkipSpiPCP;

-/** Offset 0x03AB - PMIC PCH_PWROK delay configuration - IPC Configuration
-  Upd for changing PCH_PWROK delay configuration : I2C_Slave_Address (31:24) + Register_Offset
-  (23:16) + OR Value (15:8) + AND Value (7:0)
-**/
-  UINT32                      PmicPmcIpcCtrl;
-
-/** Offset 0x03AF - ModPhyIfValue
+/** Offset 0x03AB - ModPhyIfValue
   Upd To modify the Integrated Filter (IF) value as 0x12(Default) for WIN and 0x16
   for Chrome
 **/
   UINT8                       ModPhyIfValue;

-/** Offset 0x03B0 - ModPhyVoltageBump
-  ModPhyVoltageBump. 1: enable, 0: disable
-  $EN_DIS
+/** Offset 0x03AC - PMIC PCH_PWROK delay configuration - IPC Configuration
+  Upd for changing PCH_PWROK delay configuration : I2C_Slave_Address (31:24) + Register_Offset
+  (23:16) + OR Value (15:8) + AND Value (7:0)
 **/
-  UINT8                       ModPhyVoltageBump;
+  UINT32                      PmicPmcIpcCtrl;

-/** Offset 0x03B1 - Vdd2 Voltage configuration
+/** Offset 0x03B0 - Vdd2 Voltage configuration
   Upd for changing Vdd2 Voltage configuration : I2C_Slave_Address (31:23) + Register_Offset
   (23:16) + OR Value (15:8) + AND Value (7:0)
 **/
   UINT32                      PmicVdd2Voltage;

+/** Offset 0x03B4 - ModPhyVoltageBump
+  ModPhyVoltageBump. 1: enable, 0: disable
+  $EN_DIS
+**/
+  UINT8                       ModPhyVoltageBump;
+
 /** Offset 0x03B5
 **/
-  UINT8                       ReservedFspsUpd[1];
+  UINT8                       ReservedFspsUpd[3];
 } FSP_S_CONFIG;

/** Fsp S SGX Configuration
@@ -1810,9 +1810,9 @@
 **/
   FSP_S_CONFIG                FspsConfig;

-/** Offset 0x03B6
+/** Offset 0x03B8
 **/
-  UINT8                       UnusedUpdSpace7[10];
+  UINT8                       UnusedUpdSpace7[8];

/** Offset 0x03C0
 **/