Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38452 )
Change subject: soc/intel/tigerlake: Add pinmux support ......................................................................
Patch Set 9:
(3 comments)
https://review.coreboot.org/c/coreboot/+/38452/9/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/38452/9/src/soc/intel/tigerlake/inc... PS9, Line 297: * mux for these pins.
Why? I don't understand why this is needed. We should be able to configure the pins natively. […]
Current TGL FSP configures all native function based on IP enable UPD and there is no way to skip FSP pin mux. And for these special pins like UART0, I2S4, DMIC, CnviRfReset and CnviClkreq, FSP use addtional UPD with predefined values. https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/master/ClientOneSilicon...
And we need to provide UPD for these special pins like below, otherwise FSP will abort during FSP initialization. Refer below UPD setting for these pins( UART0, I2S4, DMIC, CnviRfReset and CnviClkreq,) https://chrome-internal.googlesource.com/chromeos/third_party/coreboot-intel...
We'raised up internal feature request to bypass FSP pin mux and FSP team will provide proposal soon. The request is creating one UPD in FSPm, FSPs for bypassing pin mux so that it's working as previous platform. And we'll also discuss special pin mux like UART0, I2S4, DMIC, CnviRfReset and CnviClkreq.
https://review.coreboot.org/c/coreboot/+/38452/9/src/soc/intel/tigerlake/inc... PS9, Line 300: VER2
What does this mean?
This is defined in FSP definition. Ver2 is used for TGL LP. https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/master/ClientOneSilicon...
https://review.coreboot.org/c/coreboot/+/38452/9/src/soc/intel/tigerlake/inc... PS9, Line 301: 0x290C0201
What do these magic values represent?
According to current FSP code, it seems it's not just DW0 value but it's used for define GPIO Pad(physical pad) and native function by FSP internal pin mux logic. We'll ask more info in EDS when we discuss FSP pin mux bypassing option with FSP team.