[coreboot-gerrit] Change in coreboot[master]: soc/intel/(cnl, jsl, tgl): Enable SOC_INTEL_COMMON_BASECODE

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62843 )

Change subject: soc/intel/(cnl, jsl, tgl): Enable SOC_INTEL_COMMON_BASECODE
......................................................................

soc/intel/(cnl, jsl, tgl): Enable SOC_INTEL_COMMON_BASECODE

The patch SOC_INTEL_COMMON_BASECODE Kconfig for Comet Lake, Jasper Lake
and Tiger Lake SoCs. It allows access to intelbasecode/debug_feature.h
for Comet Lake, Jasper Lake and Tiger Lake SoCs.

TEST=Build code for Brya

Signed-off-by: Sridhar Siricilla 
Change-Id: Ie55ded673c8fa0edf2ca6789b15771bd2e56c95e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62843
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
---
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/jasperlake/Kconfig
M src/soc/intel/tigerlake/Kconfig
3 files changed, 3 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 0a61381..ddb1619 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -26,6 +26,7 @@
    select PMC_IPC_ACPI_INTERFACE if DISABLE_HECI1_AT_PRE_BOOT
    select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
    select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC if DISABLE_HECI1_AT_PRE_BOOT
+	select SOC_INTEL_COMMON_BASECODE if SOC_INTEL_CSE_LITE_SKU

config SOC_INTEL_COMETLAKE_1
    bool
diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
index e0e0c7b..53b0201 100644
--- a/src/soc/intel/jasperlake/Kconfig
+++ b/src/soc/intel/jasperlake/Kconfig
@@ -69,6 +69,7 @@
    select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
    select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
    select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
+	select SOC_INTEL_COMMON_BASECODE if SOC_INTEL_CSE_LITE_SKU

config DCACHE_RAM_BASE
    default 0xfef00000
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 265aa5f..c0cf683 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -88,6 +88,7 @@
    select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
    select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
    select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
+	select SOC_INTEL_COMMON_BASECODE if SOC_INTEL_CSE_LITE_SKU

config MAX_CPUS
    int