Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40722 )
Change subject: [WIP] Add Multiple Segment support ......................................................................
[WIP] Add Multiple Segment support
Test Patch for get feedback on design aspect
Change-Id: Ide7e97aa7c48fd0e993b248b38b2ad6ad94a21cb Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/intel/tglrvp/dsdt.asl M src/soc/intel/apollolake/systemagent.c M src/soc/intel/cannonlake/systemagent.c M src/soc/intel/common/block/acpi/acpi.c A src/soc/intel/common/block/acpi/acpi/extrahostbridge.asl A src/soc/intel/common/block/acpi/acpi/pcisegment.asl M src/soc/intel/common/block/include/intelblocks/systemagent.h M src/soc/intel/common/block/systemagent/Kconfig M src/soc/intel/common/block/systemagent/systemagent_def.h M src/soc/intel/common/block/systemagent/systemagent_early.c A src/soc/intel/common/block/tcss/Kconfig M src/soc/intel/icelake/systemagent.c M src/soc/intel/jasperlake/systemagent.c M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/systemagent.c M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/acpi/pci_irqs.asl M src/soc/intel/tigerlake/include/soc/irq.h M src/soc/intel/tigerlake/systemagent.c 19 files changed, 195 insertions(+), 51 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/40722/1
diff --git a/src/mainboard/intel/tglrvp/dsdt.asl b/src/mainboard/intel/tglrvp/dsdt.asl index af13d9f..c531baa 100644 --- a/src/mainboard/intel/tglrvp/dsdt.asl +++ b/src/mainboard/intel/tglrvp/dsdt.asl @@ -28,6 +28,9 @@ #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/tigerlake/acpi/southbridge.asl> } + #if CONFIG_SA_PCI_SEGMENT_GROUPS > 1 + #include <soc/intel/common/block/acpi/acpi/pcisegment.asl> + #endif }
#if CONFIG(CHROMEOS) diff --git a/src/soc/intel/apollolake/systemagent.c b/src/soc/intel/apollolake/systemagent.c index a1b6b4d..a15200b 100644 --- a/src/soc/intel/apollolake/systemagent.c +++ b/src/soc/intel/apollolake/systemagent.c @@ -31,7 +31,8 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index) { static const struct sa_mmio_descriptor soc_fixed_resources[] = { - { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, + { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, + PCIEXBAR_LENGTH_MiB(CONFIG_SA_PCI_SEGMENT_GROUPS), "PCIEXBAR" }, { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, }; diff --git a/src/soc/intel/cannonlake/systemagent.c b/src/soc/intel/cannonlake/systemagent.c index 1ab365e..9d7e40e 100644 --- a/src/soc/intel/cannonlake/systemagent.c +++ b/src/soc/intel/cannonlake/systemagent.c @@ -20,7 +20,8 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index) { static const struct sa_mmio_descriptor soc_fixed_resources[] = { - { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, + { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, + PCIEXBAR_LENGTH_MiB(CONFIG_SA_PCI_SEGMENT_GROUPS), "PCIEXBAR" }, { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index fe127a2..9b0457f 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -35,10 +35,13 @@
__attribute__((weak)) unsigned long acpi_fill_mcfg(unsigned long current) { - /* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */ - current += acpi_create_mcfg_mmconfig((void *)current, - CONFIG_MMCONF_BASE_ADDRESS, 0, 0, - (CONFIG_SA_PCIEX_LENGTH >> 20) - 1); + /* + * PCI Segment Group depends on CONFIG_SA_PCI_SEGMENT_GROUPS, + * Start Bus Number 0, End Bus Number is 255 + */ + for (int i = 0; i < CONFIG_SA_PCI_SEGMENT_GROUPS; i++) + current += acpi_create_mcfg_mmconfig((void *)current, + CONFIG_MMCONF_BASE_ADDRESS, i, 0, 255); return current; }
diff --git a/src/soc/intel/common/block/acpi/acpi/extrahostbridge.asl b/src/soc/intel/common/block/acpi/acpi/extrahostbridge.asl new file mode 100644 index 0000000..77c0248 --- /dev/null +++ b/src/soc/intel/common/block/acpi/acpi/extrahostbridge.asl @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method (_CRS, 0, Serialized) +{ + Name (MCRS, ResourceTemplate () + { + /* Bus Numbers */ + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100) + + /* IO Region 0 */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, + EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8) + + /* IO Region 1 */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, + EntireRange, + 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300) + + /* PCI Memory Region (TLUD - 0xdfffffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0x00000000, 0xdfffffff, 0x00000000, + 0xE0000000,,, PM01) + + /* PCI Memory Region (TUUD - (TUUD + ABOVE_4G_MMIO_SIZE)) */ + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0x10000, 0x1ffff, 0x00000000, + 0x10000,,, PM02) + }) + + /* Find PCI resource area in MCRS */ + CreateDwordField (MCRS, PM01._MIN, PMIN) + CreateDwordField (MCRS, PM01._MAX, PMAX) + CreateDwordField (MCRS, PM01._LEN, PLEN) + + /* + * Fix up PCI memory region + * Start with Top of Lower Usable DRAM + */ + Store (_SB.PCI0.MCHC.TLUD, PMIN) + Add (Subtract (PMAX, PMIN), 1, PLEN) + + /* Patch PM02 range based on Memory Size */ + If (LEqual (A4GS, 0)) { + CreateQwordField (MCRS, PM02._LEN, MSEN) + Store (0, MSEN) + } Else { + CreateQwordField (MCRS, PM02._MIN, MMIN) + CreateQwordField (MCRS, PM02._MAX, MMAX) + CreateQwordField (MCRS, PM02._LEN, MLEN) + /* Set 64bit MMIO resource base and length */ + Store (A4GS, MLEN) + Store (A4GB, MMIN) + Subtract (Add (MMIN, MLEN), 1, MMAX) + } + + Return (MCRS) +} diff --git a/src/soc/intel/common/block/acpi/acpi/pcisegment.asl b/src/soc/intel/common/block/acpi/acpi/pcisegment.asl new file mode 100644 index 0000000..4efaf20 --- /dev/null +++ b/src/soc/intel/common/block/acpi/acpi/pcisegment.asl @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define TBT_PCIe0_IRQ 16 +#define TBT_PCIe1_IRQ 17 +#define TBT_PCIe2_IRQ 18 +#define TBT_PCIe3_IRQ 19 + +Device (PCI1) +{ + Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID + Name (_SEG, 1) // _SEG: PCI Segment + Name (_UID, 1) // _UID: Unique ID + Name (_ADR, 0x00000000) + + Name (PICN, Package () { + /* SEG1: PCIe Root Port*/ + Package(){0x0007FFFF, 0, 0, 11 }, + Package(){0x0007FFFF, 1, 0, 10 }, + Package(){0x0007FFFF, 2, 0, 11 }, + Package(){0x0007FFFF, 3, 0, 11 }, + }) + + Name (PICP, Package () { + /* SEG1: PCIe Root Port*/ + Package(){0x0007FFFF, 0, 0, TBT_PCIe0_IRQ }, + Package(){0x0007FFFF, 1, 0, TBT_PCIe1_IRQ }, + Package(){0x0007FFFF, 2, 0, TBT_PCIe2_IRQ }, + Package(){0x0007FFFF, 3, 0, TBT_PCIe3_IRQ }, + }) + + Method (_PRT) + { + If (PICM) { + Return (PICP) + } Else { + Return (PICN) + } + } + #include "extrahostbridge.asl" +} diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h index c6aa4b4..cfa96e3 100644 --- a/src/soc/intel/common/block/include/intelblocks/systemagent.h +++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h @@ -4,11 +4,14 @@ #ifndef SOC_INTEL_COMMON_BLOCK_SA_H #define SOC_INTEL_COMMON_BLOCK_SA_H
+#include <commonlib/helpers.h> #include <device/device.h> #include <soc/iomap.h> #include <soc/nvs.h> #include <stddef.h>
+#define PCIEXBAR_LENGTH_MiB(x) (x * 256 * MiB) + /* Device 0:0.0 PCI configuration space */ #define MCHBAR 0x48 #define PCIEXBAR 0x60 diff --git a/src/soc/intel/common/block/systemagent/Kconfig b/src/soc/intel/common/block/systemagent/Kconfig index 6dd1f3b..759abc9 100644 --- a/src/soc/intel/common/block/systemagent/Kconfig +++ b/src/soc/intel/common/block/systemagent/Kconfig @@ -9,23 +9,18 @@ hex default 0xe0000000
-config SA_PCIEX_LENGTH +config SA_PCI_SEGMENT_GROUPS hex - default 0x10000000 if (PCIEX_LENGTH_256MB) - default 0x8000000 if (PCIEX_LENGTH_128MB) - default 0x4000000 if (PCIEX_LENGTH_64MB) - default 0x10000000 + default 1 + default 2 if TCSS_PCIE_SEGMENT help - This option allows you to select length of PCIEX region. + This option allows you to select required PCI segment.
-config PCIEX_LENGTH_256MB - bool - -config PCIEX_LENGTH_128MB - bool - -config PCIEX_LENGTH_64MB - bool + Each PCI segment supports up to 256 buses (0-255). + PCIE length selection is depends on PCI_SEGMENT_GROUPS. + Formula for PCIE Length = PCI_SEGMENT_GROUPS * 256 MB + If PCI segment is 1 then length of PCIEX region is 256MB to support 256 buses + else PCIEX region would be multiple of 256MB based on PCI_SEGMENT_GROUPS.
config SA_ENABLE_IMR bool diff --git a/src/soc/intel/common/block/systemagent/systemagent_def.h b/src/soc/intel/common/block/systemagent/systemagent_def.h index 03f4de4..ef2f7b4 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_def.h +++ b/src/soc/intel/common/block/systemagent/systemagent_def.h @@ -4,7 +4,6 @@ #ifndef SOC_INTEL_COMMON_BLOCK_SA_DEF_H #define SOC_INTEL_COMMON_BLOCK_SA_DEF_H
- /* Device 0:0.0 PCI configuration space */
/* GMCH Graphics Control Register */ @@ -19,8 +18,10 @@ #define DPR_PRS (1 << 1) #define DPR_SIZE_MASK 0xff0
-#define PCIEXBAR_LENGTH_64MB 2 -#define PCIEXBAR_LENGTH_128MB 1 +#define PCIEXBAR_LENGTH_4096MB 6 +#define PCIEXBAR_LENGTH_2048MB 5 +#define PCIEXBAR_LENGTH_1024MB 4 +#define PCIEXBAR_LENGTH_512MB 3 #define PCIEXBAR_LENGTH_256MB 0 #define PCIEXBAR_PCIEXBAREN (1 << 0)
diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index cb0ed34..69b36f8 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -27,15 +27,21 @@ pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, reg);
/* Get PCI Express Region Length */ - switch (CONFIG_SA_PCIEX_LENGTH) { - case 256 * MiB: + switch (CONFIG_SA_PCI_SEGMENT_GROUPS) { + case 1: pciexbar_length = PCIEXBAR_LENGTH_256MB; break; - case 128 * MiB: - pciexbar_length = PCIEXBAR_LENGTH_128MB; + case 2: + pciexbar_length = PCIEXBAR_LENGTH_512MB; break; - case 64 * MiB: - pciexbar_length = PCIEXBAR_LENGTH_64MB; + case 4: + pciexbar_length = PCIEXBAR_LENGTH_1024MB; + break; + case 8: + pciexbar_length = PCIEXBAR_LENGTH_2048MB; + break; + case 16: + pciexbar_length = PCIEXBAR_LENGTH_4096MB; break; default: pciexbar_length = PCIEXBAR_LENGTH_256MB; diff --git a/src/soc/intel/common/block/tcss/Kconfig b/src/soc/intel/common/block/tcss/Kconfig new file mode 100644 index 0000000..0f7fe7c --- /dev/null +++ b/src/soc/intel/common/block/tcss/Kconfig @@ -0,0 +1,9 @@ +config SOC_INTEL_COMMON_BLOCK_TCSS + bool + help + Intel Processor common TCSS support + +config TCSS_PCIE_SEGMENT + bool + help + Indicate the extra PCIE segment is required for iTBT or not diff --git a/src/soc/intel/icelake/systemagent.c b/src/soc/intel/icelake/systemagent.c index c07fd0a..6cf6354 100644 --- a/src/soc/intel/icelake/systemagent.c +++ b/src/soc/intel/icelake/systemagent.c @@ -16,7 +16,8 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index) { static const struct sa_mmio_descriptor soc_fixed_resources[] = { - { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, + { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, + PCIEXBAR_LENGTH_MiB(CONFIG_SA_PCI_SEGMENT_GROUPS), "PCIEXBAR" }, { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, diff --git a/src/soc/intel/jasperlake/systemagent.c b/src/soc/intel/jasperlake/systemagent.c index 7be471a..4c5efe7 100644 --- a/src/soc/intel/jasperlake/systemagent.c +++ b/src/soc/intel/jasperlake/systemagent.c @@ -17,7 +17,8 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index) { static const struct sa_mmio_descriptor soc_fixed_resources[] = { - { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, + { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, + PCIEXBAR_LENGTH_MiB(CONFIG_SA_PCI_SEGMENT_GROUPS), "PCIEXBAR" }, { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 75f6b69..5d95029 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -200,9 +200,13 @@
unsigned long acpi_fill_mcfg(unsigned long current) { - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, - CONFIG_MMCONF_BASE_ADDRESS, 0, 0, - (CONFIG_SA_PCIEX_LENGTH >> 20) - 1); + /* + * PCI Segment Group depends on CONFIG_SA_PCI_SEGMENT_GROUPS, + * Start Bus Number 0, End Bus Number is 255 + */ + for (int i = 0; i < CONFIG_SA_PCI_SEGMENT_GROUPS; i++) + current += acpi_create_mcfg_mmconfig((void *)current, + CONFIG_MMCONF_BASE_ADDRESS, i, 0, 255); return current; }
diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c index 9a4c4de..a71dbb2 100644 --- a/src/soc/intel/skylake/systemagent.c +++ b/src/soc/intel/skylake/systemagent.c @@ -31,7 +31,8 @@ struct device *const igd_dev = pcidev_path_on_root(SA_DEVFN_IGD);
static const struct sa_mmio_descriptor soc_fixed_resources[] = { - { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, + { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, + PCIEXBAR_LENGTH_MiB(CONFIG_SA_PCI_SEGMENT_GROUPS), "PCIEXBAR" }, { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index a690acf..93f12f9 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -60,6 +60,7 @@ select UDK_2017_BINDING select DISPLAY_FSP_VERSION_INFO select HECI_DISABLE_USING_SMM + select TCSS_PCIE_SEGMENT
config DCACHE_RAM_BASE default 0xfef00000 diff --git a/src/soc/intel/tigerlake/acpi/pci_irqs.asl b/src/soc/intel/tigerlake/acpi/pci_irqs.asl index 62520b1..7603362 100644 --- a/src/soc/intel/tigerlake/acpi/pci_irqs.asl +++ b/src/soc/intel/tigerlake/acpi/pci_irqs.asl @@ -73,11 +73,6 @@ Package(){0x000DFFFF, 1, 0, xDCI_IRQ }, /* D8: GNA */ Package(){0x0008FFFF, 0, 0, GNA_IRQ }, - /* D7: TBT PCIe */ - Package(){0x0007FFFF, 0, 0, TBT_PCIe0_IRQ }, - Package(){0x0007FFFF, 1, 0, TBT_PCIe1_IRQ }, - Package(){0x0007FFFF, 2, 0, TBT_PCIe2_IRQ }, - Package(){0x0007FFFF, 3, 0, TBT_PCIe3_IRQ }, /* D6: PEG60 */ Package(){0x0006FFFF, 0, 0, PEG_IRQ }, /* D5: IPU Device */ @@ -142,11 +137,6 @@ Package(){0x000DFFFF, 1, 0, 10 }, /* D8: GNA */ Package(){0x0008FFFF, 0, 0, 11 }, - /* D7: TBT PCIe */ - Package(){0x0007FFFF, 0, 0, 11 }, - Package(){0x0007FFFF, 1, 0, 10 }, - Package(){0x0007FFFF, 2, 0, 11 }, - Package(){0x0007FFFF, 3, 0, 11 }, /* D6: PEG60 */ Package(){0x0006FFFF, 0, 0, 11 }, /* D5: IPU Device */ diff --git a/src/soc/intel/tigerlake/include/soc/irq.h b/src/soc/intel/tigerlake/include/soc/irq.h index 01ee10b..1057f91 100644 --- a/src/soc/intel/tigerlake/include/soc/irq.h +++ b/src/soc/intel/tigerlake/include/soc/irq.h @@ -54,11 +54,6 @@
#define ISH_IRQ 16
-#define TBT_PCIe0_IRQ 16 -#define TBT_PCIe1_IRQ 17 -#define TBT_PCIe2_IRQ 18 -#define TBT_PCIe3_IRQ 19 - #define HECI_1_IRQ 16 #define HECI_2_IRQ 17 #define HECI_3_IRQ 16 diff --git a/src/soc/intel/tigerlake/systemagent.c b/src/soc/intel/tigerlake/systemagent.c index 8859386..a6d7ae8 100644 --- a/src/soc/intel/tigerlake/systemagent.c +++ b/src/soc/intel/tigerlake/systemagent.c @@ -23,7 +23,8 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index) { static const struct sa_mmio_descriptor soc_fixed_resources[] = { - { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, + { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, + PCIEXBAR_LENGTH_MiB(CONFIG_SA_PCI_SEGMENT_GROUPS), "PCIEXBAR" }, { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },