Tristan Corrick has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29977 )
Change subject: sb/intel/common: Create a common PCH finalise implementation ......................................................................
Patch Set 3:
(4 comments)
https://review.coreboot.org/#/c/29977/2/src/southbridge/intel/common/finaliz... File src/southbridge/intel/common/finalize.c:
https://review.coreboot.org/#/c/29977/2/src/southbridge/intel/common/finaliz... PS2, Line 75: outb(POST_OS_BOOT, 0x80);
The name is just misleading. You might want to change that instead […]
Done
https://review.coreboot.org/#/c/29977/2/src/southbridge/intel/common/finaliz... PS2, Line 61:
It was just called differently: PMIR (same location).
Okay, thanks.
https://review.coreboot.org/#/c/29977/2/src/southbridge/intel/common/finaliz... PS2, Line 62: pci_update_config32(lpc_dev, D31F0_ETR3, ~ETR3_CF9GR, ETR3_CF9LOCK); : : if (IS_ENABLED(CONFIG_SOUTHBRID
It's HSW only. […]
Done
https://review.coreboot.org/#/c/29977/2/src/southbridge/intel/common/pmutil.... File src/southbridge/intel/common/pmutil.h:
https://review.coreboot.org/#/c/29977/2/src/southbridge/intel/common/pmutil.... PS2, Line 25: F
F
Done