Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46418 )
Change subject: mb/intel/adlrvp: Fix SSD detection issue on ADL RVP ......................................................................
mb/intel/adlrvp: Fix SSD detection issue on ADL RVP
Make PCI ClkReq-to-ClkSrc mapping correct to fix SSD detection issue on ADL RVP.
TEST=Able to detect WD SSD card over PCH SSD RP9.
Change-Id: I7e26429281f8d3b9edae0f266a5868118369be3f Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46418 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb 1 file changed, 2 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb index 7025b76..afa4c19 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb @@ -43,7 +43,7 @@
# Enable PCH PCIE RP 5 using CLK 2 register "PcieRpEnable[4]" = "1" - register "PcieClkSrcClkReq[4]" = "4" + register "PcieClkSrcClkReq[2]" = "2" register "PcieClkSrcUsage[2]" = "0x4" register "PcieRpClkReqDetect[4]" = "1"
@@ -55,7 +55,7 @@
# Enable PCH PCIE RP 9 using CLK 1 register "PcieRpEnable[8]" = "1" - register "PcieClkSrcClkReq[8]" = "8" + register "PcieClkSrcClkReq[1]" = "1" register "PcieClkSrcUsage[1]" = "0x8" register "PcieRpClkReqDetect[8]" = "1"