[coreboot-gerrit] Change in coreboot[master]: soc/skylake: Write the P2SB IBDF and HBDF registers in coreboot

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35170 )

Change subject: soc/skylake: Write the P2SB IBDF and HBDF registers in coreboot
......................................................................

soc/skylake: Write the P2SB IBDF and HBDF registers in coreboot

Do it in coreboot code instead of letting FSP do it.

Change-Id: Ic5e8a62141608463ade398432253bad460a9a79d
Signed-off-by: Angel Pons 
---
M src/soc/intel/skylake/bootblock/pch.c
M src/soc/intel/skylake/chip_fsp20.c
M src/soc/intel/skylake/include/soc/systemagent.h
M src/soc/intel/skylake/romstage/romstage_fsp20.c
4 files changed, 13 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/35170/1

diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
index c95a8d8..740ce89 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -35,6 +35,7 @@
 #include <soc/pm.h>
 #include <soc/pmc.h>
 #include <soc/smbus.h>
+#include <soc/systemagent.h>

#include "../chip.h"

@@ -50,6 +51,12 @@
    fast_spi_early_init(SPI_BASE_ADDRESS);
    p2sb_enable_bar();
    p2sb_configure_hpet();
+
+	/* Write the IOAPIC Bus:Dev.Fun value to P2SB IBDF register */
+	pci_write_config16(PCH_DEV_P2SB, PCH_P2SB_IBDF, V_DEFAULT_IBDF);
+
+	/* Write the HPET Bus:Dev.Fun value to P2SB HBDF register */
+	pci_write_config16(PCH_DEV_P2SB, PCH_P2SB_HBDF, V_DEFAULT_HBDF);
 }

static void soc_config_acpibase(void)
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index 43bf27c..ed33c20 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -484,10 +484,8 @@
    	params->X2ApicOptOut = 0;
    	tconfig->VtdDisable = 0;

-		params->PchIoApicBdfValid = 1;
-		params->PchIoApicBusNumber = V_P2SB_IBDF_BUS;
-		params->PchIoApicDeviceNumber = V_P2SB_IBDF_DEV;
-		params->PchIoApicFunctionNumber = V_P2SB_IBDF_FUN;
+		/* HPET Bus:Dev.Fun already set in coreboot, so tell FSP to ignore UPDs */
+		params->PchIoApicBdfValid = 0;
    }

soc_irq_settings(params);
diff --git a/src/soc/intel/skylake/include/soc/systemagent.h b/src/soc/intel/skylake/include/soc/systemagent.h
index 565c885..91209c8 100644
--- a/src/soc/intel/skylake/include/soc/systemagent.h
+++ b/src/soc/intel/skylake/include/soc/systemagent.h
@@ -66,9 +66,11 @@
 #define V_P2SB_IBDF_BUS	250
 #define V_P2SB_IBDF_DEV	31
 #define V_P2SB_IBDF_FUN	0
+#define V_DEFAULT_IBDF	((V_P2SB_IBDF_BUS << 8) | PCI_DEVFN(V_P2SB_IBDF_DEV, V_P2SB_IBDF_FUN))

#define V_P2SB_HBDF_BUS	250
 #define V_P2SB_HBDF_DEV	15
 #define V_P2SB_HBDF_FUN	0
+#define V_DEFAULT_HBDF	((V_P2SB_HBDF_BUS << 8) | PCI_DEVFN(V_P2SB_HBDF_DEV, V_P2SB_HBDF_FUN))

#endif
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index 4844660..a4d1d50 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -246,10 +246,8 @@
    cpu_flex_override(m_cfg);

if (!config->ignore_vtd) {
-		m_cfg->PchHpetBdfValid = 1;
-		m_cfg->PchHpetBusNumber = V_P2SB_HBDF_BUS;
-		m_cfg->PchHpetDeviceNumber = V_P2SB_HBDF_DEV;
-		m_cfg->PchHpetFunctionNumber = V_P2SB_HBDF_FUN;
+		/* HPET Bus:Dev.Fun already set in coreboot, so tell FSP to ignore UPDs */
+		m_cfg->PchHpetBdfValid = 0;
    }
 }