[coreboot-gerrit] Patch set updated for coreboot: mainboard/*/*/mptable.c: Improve code formatting

[HAOUAS Elyes]

HAOUAS Elyes ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16723

-gerrit

commit 494e4c3d13e1a02b2af44b0c8de29259dd6533f4
Author: Elyes HAOUAS 
Date:   Thu Sep 22 21:20:54 2016 +0200

mainboard/*/*/mptable.c: Improve code formatting

Change-Id: I341293cd334d6d465636db7e81400230d61bc693
    Signed-off-by: Elyes HAOUAS 
---
 src/mainboard/amd/bettong/mptable.c            |   2 +-
 src/mainboard/amd/db-ft3b-lc/mptable.c         |   2 +-
 src/mainboard/amd/olivehill/mptable.c          |   2 +-
 src/mainboard/amd/olivehillplus/mptable.c      |   2 +-
 src/mainboard/amd/parmer/mptable.c             |   2 +-
 src/mainboard/amd/serengeti_cheetah/mptable.c  | 180 ++++++------
 src/mainboard/amd/south_station/mptable.c      | 130 ++++-----
 src/mainboard/amd/thatcher/mptable.c           |   2 +-
 src/mainboard/amd/torpedo/mptable.c            | 370 ++++++++++++-------------
 src/mainboard/amd/union_station/mptable.c      | 132 ++++-----
 src/mainboard/apple/macbook21/mptable.c        |   6 +-
 src/mainboard/asrock/e350m1/mptable.c          | 130 ++++-----
 src/mainboard/asrock/imb-a180/mptable.c        |   2 +-
 src/mainboard/asus/f2a85-m/mptable.c           |   2 +-
 src/mainboard/bap/ode_e21XX/mptable.c          |   2 +-
 src/mainboard/broadcom/blast/mptable.c         | 110 ++++----
 src/mainboard/getac/p470/mptable.c             |   6 +-
 src/mainboard/gigabyte/ga_2761gxdk/mptable.c   |  56 ++--
 src/mainboard/gigabyte/m57sli/mptable.c        |  60 ++--
 src/mainboard/hp/abm/mptable.c                 |   2 +-
 src/mainboard/hp/pavilion_m6_1035dx/mptable.c  |   2 +-
 src/mainboard/ibase/mb899/mptable.c            |   6 +-
 src/mainboard/intel/d945gclf/mptable.c         |   6 +-
 src/mainboard/intel/eagleheights/mptable.c     |  78 +++---
 src/mainboard/kontron/986lcd-m/mptable.c       |   6 +-
 src/mainboard/lenovo/g505s/mptable.c           |   2 +-
 src/mainboard/lenovo/t60/mptable.c             |   6 +-
 src/mainboard/lenovo/x60/mptable.c             |   6 +-
 src/mainboard/msi/ms9185/mptable.c             | 140 +++++-----
 src/mainboard/roda/rk886ex/mptable.c           |   6 +-
 src/mainboard/siemens/sitemp_g1p1/mptable.c    |   2 +-
 src/mainboard/sunw/ultra40/mptable.c           | 176 ++++++------
 src/mainboard/supermicro/h8dme/mptable.c       |  56 ++--
 src/mainboard/supermicro/h8dmr/mptable.c       |  56 ++--
 src/mainboard/supermicro/h8dmr_fam10/mptable.c |   2 +-
 35 files changed, 875 insertions(+), 875 deletions(-)

diff --git a/src/mainboard/amd/bettong/mptable.c b/src/mainboard/amd/bettong/mptable.c
index 1c74ae5..744fd98 100644
--- a/src/mainboard/amd/bettong/mptable.c
+++ b/src/mainboard/amd/bettong/mptable.c
@@ -84,7 +84,7 @@ static void *smp_write_config_table(void *v)
     * associated with a specific bus/device/function tuple.
     */
 #define PCI_INT(bus, dev, int_sign, pin)				\
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))

/* Internal VGA */
    PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
diff --git a/src/mainboard/amd/db-ft3b-lc/mptable.c b/src/mainboard/amd/db-ft3b-lc/mptable.c
index 0c668df..dac3897 100644
--- a/src/mainboard/amd/db-ft3b-lc/mptable.c
+++ b/src/mainboard/amd/db-ft3b-lc/mptable.c
@@ -75,7 +75,7 @@ static void *smp_write_config_table(void *v)
     * associated with a specific bus/device/function tuple.
     */
 #define PCI_INT(bus, dev, int_sign, pin)				\
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))

/* APU Internal Graphic Device */
    PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c
index 50d1aa3..9ae75ae 100644
--- a/src/mainboard/amd/olivehill/mptable.c
+++ b/src/mainboard/amd/olivehill/mptable.c
@@ -150,7 +150,7 @@ static void *smp_write_config_table(void *v)
     * associated with a specific bus/device/function tuple.
     */
 #define PCI_INT(bus, dev, int_sign, pin)				\
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))

/* Internal VGA */
    PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/amd/olivehillplus/mptable.c b/src/mainboard/amd/olivehillplus/mptable.c
index a2ba7f4..925526c 100644
--- a/src/mainboard/amd/olivehillplus/mptable.c
+++ b/src/mainboard/amd/olivehillplus/mptable.c
@@ -111,7 +111,7 @@ static void *smp_write_config_table(void *v)
     * associated with a specific bus/device/function tuple.
     */
 #define PCI_INT(bus, dev, int_sign, pin)				\
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))

/* Internal VGA */
    PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c
index 8f226d5..e10fc89 100644
--- a/src/mainboard/amd/parmer/mptable.c
+++ b/src/mainboard/amd/parmer/mptable.c
@@ -111,7 +111,7 @@ static void *smp_write_config_table(void *v)
     * associated with a specific bus/device/function tuple.
     */
 #define PCI_INT(bus, dev, int_sign, pin)				\
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))

/* Internal VGA */
    PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/amd/serengeti_cheetah/mptable.c b/src/mainboard/amd/serengeti_cheetah/mptable.c
index acc4a6c..2ffe4c9 100644
--- a/src/mainboard/amd/serengeti_cheetah/mptable.c
+++ b/src/mainboard/amd/serengeti_cheetah/mptable.c
@@ -25,15 +25,15 @@

static void *smp_write_config_table(void *v)
 {
-        struct mp_config_table *mc;
+	struct mp_config_table *mc;
    int i, j, bus_isa;
    struct mb_sysconf_t *m;

-        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);

mptable_init(mc, LOCAL_APIC_ADDR);

-        smp_write_processors(mc);
+	smp_write_processors(mc);

get_bus_conf();

@@ -43,54 +43,54 @@ static void *smp_write_config_table(void *v)

/*I/O APICs:	APIC ID	Version	State		Address*/
    smp_write_ioapic(mc, m->apicid_8111, 0x11, VIO_APIC_VADDR); //8111
-        {
-                device_t dev;
+	{
+		device_t dev;
    	struct resource *res;
-                dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1));
-                if (dev) {
+		dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1));
+		if (dev) {
    		res = find_resource(dev, PCI_BASE_ADDRESS_0);
    		if (res) {
    			smp_write_ioapic(mc, m->apicid_8132_1, 0x11,
    					 res2mmio(res, 0, 0));
    		}
-                }
-                dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1));
-                if (dev) {
+		}
+		dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1));
+		if (dev) {
    		res = find_resource(dev, PCI_BASE_ADDRESS_0);
    		if (res) {
    			smp_write_ioapic(mc, m->apicid_8132_2, 0x11,
    					 res2mmio(res, 0, 0));
    		}
-                }
+		}

-                j = 0;
+		j = 0;

-                for(i = 1; i< sysconf.hc_possible_num; i++) {
-                        if(!(sysconf.pci1234[i] & 0x1) ) continue;
+		for(i = 1; i< sysconf.hc_possible_num; i++) {
+			if(!(sysconf.pci1234[i] & 0x1) ) continue;

-                        switch(sysconf.hcid[i]) {
-                        case 1: // 8132
+			switch(sysconf.hcid[i]) {
+			case 1: // 8132
    		case 3: // 8131
-                                dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
-                                if (dev) {
-                                        res = find_resource(dev, PCI_BASE_ADDRESS_0);
-                                        if (res) {
-                                                smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11,
+				dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
+				if (dev) {
+					res = find_resource(dev, PCI_BASE_ADDRESS_0);
+					if (res) {
+						smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11,
    							 res2mmio(res, 0, 0));
-                                        }
-                                }
-                                dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
-                                if (dev) {
-                                        res = find_resource(dev, PCI_BASE_ADDRESS_0);
-                                        if (res) {
-                                                smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11,
+					}
+				}
+				dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
+				if (dev) {
+					res = find_resource(dev, PCI_BASE_ADDRESS_0);
+					if (res) {
+						smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11,
    							 res2mmio(res, 0, 0));
-                                        }
-                                }
-                                break;
-                        }
-                        j++;
-                }
+					}
+				}
+				break;
+			}
+			j++;
+		}

}

@@ -98,76 +98,76 @@ static void *smp_write_config_table(void *v)

/*I/O Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN# */
 //??? What
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13);

// Onboard AMD USB
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0 << 2)|3, m->apicid_8111, 0x13);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0 << 2)|3, m->apicid_8111, 0x13);

//Slot 3  PCI 32
-        for(i = 0; i < 4; i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5 << 2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16
-        }
+	for(i = 0; i < 4; i++) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5 << 2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16
+	}

//Slot 4 PCI 32
-        for(i = 0; i < 4; i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4 << 2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16
-        }
+	for(i = 0; i < 4; i++) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4 << 2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16
+	}

//Slot 1 PCI-X 133/100/66
-        for(i = 0; i < 4; i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1 << 2)|i, m->apicid_8132_2, (0+i)%4); //
-        }
+	for(i = 0; i < 4; i++) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1 << 2)|i, m->apicid_8132_2, (0+i)%4); //
+	}

//Slot 2 PCI-X 133/100/66
-        for(i = 0; i < 4; i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1 << 2)|i, m->apicid_8132_1, (1+i)%4); //25
-        }
-
-        j = 0;
-
-        for(i = 1; i< sysconf.hc_possible_num; i++) {
-                if(!(sysconf.pci1234[i] & 0x1) ) continue;
-                int ii;
-                device_t dev;
-                struct resource *res;
-                switch(sysconf.hcid[i]) {
-                case 1:
+	for(i = 0; i < 4; i++) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1 << 2)|i, m->apicid_8132_1, (1+i)%4); //25
+	}
+
+	j = 0;
+
+	for(i = 1; i< sysconf.hc_possible_num; i++) {
+		if(!(sysconf.pci1234[i] & 0x1) ) continue;
+		int ii;
+		device_t dev;
+		struct resource *res;
+		switch(sysconf.hcid[i]) {
+		case 1:
    	case 3:
-                        dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
-                        if (dev) {
-                                res = find_resource(dev, PCI_BASE_ADDRESS_0);
-                                if (res) {
-                                        //Slot 1 PCI-X 133/100/66
-                                        for(ii = 0; ii < 4; ii++) {
-                                                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0 << 2)|ii, m->apicid_8132a[j][0], (0+ii)%4); //
-                                        }
-                                }
-                        }
-
-                        dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
-                        if (dev) {
-                                res = find_resource(dev, PCI_BASE_ADDRESS_0);
-                                if (res) {
-                                        //Slot 2 PCI-X 133/100/66
-                                        for(ii = 0; ii < 4; ii++) {
-                                                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0 << 2)|ii, m->apicid_8132a[j][1], (0+ii)%4); //25
-                                        }
-                                }
-                        }
-
-                        break;
-                case 2:
-
-                //  Slot AGP
-                        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11);
-                        break;
-                }
-
-                j++;
-        }
+			dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
+			if (dev) {
+				res = find_resource(dev, PCI_BASE_ADDRESS_0);
+				if (res) {
+					//Slot 1 PCI-X 133/100/66
+					for(ii = 0; ii < 4; ii++) {
+						smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0 << 2)|ii, m->apicid_8132a[j][0], (0+ii)%4); //
+					}
+				}
+			}
+
+			dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
+			if (dev) {
+				res = find_resource(dev, PCI_BASE_ADDRESS_0);
+				if (res) {
+					//Slot 2 PCI-X 133/100/66
+					for(ii = 0; ii < 4; ii++) {
+						smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0 << 2)|ii, m->apicid_8132a[j][1], (0+ii)%4); //25
+					}
+				}
+			}
+
+			break;
+		case 2:
+
+		//  Slot AGP
+			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11);
+			break;
+		}
+
+		j++;
+	}

diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c
index 19a9f35..c24e42c 100644
--- a/src/mainboard/amd/south_station/mptable.c
+++ b/src/mainboard/amd/south_station/mptable.c
@@ -26,81 +26,81 @@

u8 intr_data[] = {
-  [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
-  [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
-  [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x10,0x11,0x12,0x13
+	[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
+	[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
+	[0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x10,0x11,0x12,0x13
 };

static void *smp_write_config_table(void *v)
 {
-  struct mp_config_table *mc;
-  int bus_isa;
+	struct mp_config_table *mc;
+	int bus_isa;

/*
     * By the time this function gets called, the IOAPIC registers
     * have been written so they can be read to get the correct
     * APIC ID and Version
     */
-  u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
-  u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
+	u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
+	u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);

-  mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);

-  mptable_init(mc, LOCAL_APIC_ADDR);
-  memcpy(mc->mpc_oem, "AMD     ", 8);
+	mptable_init(mc, LOCAL_APIC_ADDR);
+	memcpy(mc->mpc_oem, "AMD     ", 8);

-  smp_write_processors(mc);
+	smp_write_processors(mc);

-  mptable_write_buses(mc, NULL, &bus_isa);
+	mptable_write_buses(mc, NULL, &bus_isa);

-  /* I/O APICs:   APIC ID Version State   Address */
+	/* I/O APICs:   APIC ID Version State   Address */
    smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);

-  u8 byte;
+	u8 byte;

-  for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
-    outb(byte | 0x80, 0xC00);
-    outb(intr_data[byte], 0xC01);
-  }
+	for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
+		outb(byte | 0x80, 0xC00);
+		outb(intr_data[byte], 0xC01);
+	}

-  /* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
+	/* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
 #define IO_LOCAL_INT(type, intr, apicid, pin) \
-  smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+	smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));

-  mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
+	mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);

-  /* PCI interrupts are level triggered, and are
-   * associated with a specific bus/device/function tuple.
-   */
+	/* PCI interrupts are level triggered, and are
+	 * associated with a specific bus/device/function tuple.
+	 */
 #define PCI_INT(bus, dev, fn, pin) \
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))

-  /* APU Internal Graphic Device*/
-  PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
-  PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+	/* APU Internal Graphic Device*/
+	PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
+	PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);

-  //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
-  PCI_INT(0x0, 0x14, 0x0, 0x10);
-  /* Southbridge HD Audio: */
-  PCI_INT(0x0, 0x14, 0x2, 0x12);
+	//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
+	PCI_INT(0x0, 0x14, 0x0, 0x10);
+	/* Southbridge HD Audio: */
+	PCI_INT(0x0, 0x14, 0x2, 0x12);

-  PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
-  PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
-  PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
-  PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
-  PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
-  PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
+	PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
+	PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
+	PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
+	PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
+	PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
+	PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);

-  /* sata */
-  PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+	/* sata */
+	PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);

-  /* on board NIC & Slot PCIE.  */
+	/* on board NIC & Slot PCIE.  */

-  /* PCI slots */
+	/* PCI slots */
    device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
    if (dev && dev->enabled) {
    	u8 bus_pci = dev->link_list->secondary;
@@ -123,27 +123,27 @@ static void *smp_write_config_table(void *v)
    	PCI_INT(bus_pci, 0x7, 0x3, 0x15);
    }

-  /* PCIe PortA */
-  PCI_INT(0x0, 0x15, 0x0, 0x10);
-  /* PCIe PortB */
-  PCI_INT(0x0, 0x15, 0x1, 0x11);
-  /* PCIe PortC */
-  PCI_INT(0x0, 0x15, 0x2, 0x12);
-  /* PCIe PortD */
-  PCI_INT(0x0, 0x15, 0x3, 0x13);
-
-  /*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
-  IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
-  IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
-  /* There is no extension information... */
-
-  /* Compute the checksums */
-  return mptable_finalize(mc);
+	/* PCIe PortA */
+	PCI_INT(0x0, 0x15, 0x0, 0x10);
+	/* PCIe PortB */
+	PCI_INT(0x0, 0x15, 0x1, 0x11);
+	/* PCIe PortC */
+	PCI_INT(0x0, 0x15, 0x2, 0x12);
+	/* PCIe PortD */
+	PCI_INT(0x0, 0x15, 0x3, 0x13);
+
+	/*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
+	IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
+	IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
+	/* There is no extension information... */
+
+	/* Compute the checksums */
+	return mptable_finalize(mc);
 }

unsigned long write_smp_table(unsigned long addr)
 {
-  void *v;
-  v = smp_write_floating_table(addr, 0);
-  return (unsigned long)smp_write_config_table(v);
+	void *v;
+	v = smp_write_floating_table(addr, 0);
+	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c
index 797f679..2640284 100644
--- a/src/mainboard/amd/thatcher/mptable.c
+++ b/src/mainboard/amd/thatcher/mptable.c
@@ -111,7 +111,7 @@ static void *smp_write_config_table(void *v)
     * associated with a specific bus/device/function tuple.
     */
 #define PCI_INT(bus, dev, int_sign, pin)				\
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))

/* Internal VGA */
    PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c
index c5c908d..8091ffb 100644
--- a/src/mainboard/amd/torpedo/mptable.c
+++ b/src/mainboard/amd/torpedo/mptable.c
@@ -25,210 +25,210 @@
 #include <cpu/amd/amdfam12.h>
 #include "SbPlatform.h"

-#define IO_APIC_ID    CONFIG_MAX_CPUS
+#define IO_APIC_ID CONFIG_MAX_CPUS
 u32 apicid_sb900;

u8 picr_data[] = {
-  0x0B,0x0B,0x0B,0x0B,0x1F,0x1F,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
-  0x09,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x0B,0x0B,0x0B,0x0B,0x0B,0x0B,0x0B,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x0B,0x0B,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x0B,0x0B,0x0B,0x0B
+	0x0B,0x0B,0x0B,0x0B,0x1F,0x1F,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+	0x09,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x0B,0x0B,0x0B,0x0B,0x0B,0x0B,0x0B,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x0B,0x0B,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x0B,0x0B,0x0B,0x0B
 };
 u8 intr_data[] = {
-  0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
-  0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x10,0x11,0x12,0x13
+	0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+	0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x10,0x11,0x12,0x13
 };

static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length)
 {
-  mc->mpc_length += length;
-  mc->mpc_entry_count++;
+	mc->mpc_length += length;
+	mc->mpc_entry_count++;
 }
 static void my_smp_write_bus(struct mp_config_table *mc,
-  unsigned char id, const char *bustype)
+	unsigned char id, const char *bustype)
 {
-  struct mpc_config_bus *mpc;
-  mpc = smp_next_mpc_entry(mc);
-  memset(mpc, '\0', sizeof(*mpc));
-  mpc->mpc_type = MP_BUS;
-  mpc->mpc_busid = id;
-  memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
-  smp_add_mpc_entry(mc, sizeof(*mpc));
+	struct mpc_config_bus *mpc;
+	mpc = smp_next_mpc_entry(mc);
+	memset(mpc, '\0', sizeof(*mpc));
+	mpc->mpc_type = MP_BUS;
+	mpc->mpc_busid = id;
+	memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
+	smp_add_mpc_entry(mc, sizeof(*mpc));
 }
 static void *smp_write_config_table(void *v)
 {
-  struct mp_config_table *mc;
-  int bus_isa;
-  int boot_apic_id;
-  unsigned apic_version;
-  unsigned cpu_features;
-  unsigned cpu_feature_flags;
-  struct cpuid_result result;
-  unsigned long cpu_flag;
-
-  mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
-  mptable_init(mc, LOCAL_APIC_ADDR);
-  memcpy(mc->mpc_oem, "AMD     ", 8);
-
-  /*Inagua used dure core CPU with one die */
-  boot_apic_id = lapicid();
-  apic_version = lapic_read(LAPIC_LVR) & 0xff;
-  result = cpuid(1);
-  cpu_features = result.eax;
-  cpu_feature_flags = result.edx;
-  cpu_flag = MPC_CPU_ENABLED | MPC_CPU_BOOTPROCESSOR;
-  smp_write_processor(mc,
-      0, apic_version,
-      cpu_flag, cpu_features, cpu_feature_flags
-    );
-
-  cpu_flag = MPC_CPU_ENABLED;
-  smp_write_processor(mc,
-      1, apic_version,
-      cpu_flag, cpu_features, cpu_feature_flags
-    );
-
-  //mptable_write_buses(mc, NULL, &bus_isa);
-  my_smp_write_bus(mc, 0, "PCI   ");
-  my_smp_write_bus(mc, 1, "PCI   ");
-  bus_isa = 0x02;
-  my_smp_write_bus(mc, bus_isa, "ISA   ");
-
-  /* I/O APICs:   APIC ID Version State   Address */
-
-  u8 *dword;
-  u8 byte;
-
-  ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
-  dword = (u8 *)(((uintptr_t) dword) & 0xFFFFFFF0);
-  /* Set IO APIC ID onto IO_APIC_ID */
-  write32 (dword, 0x00);
-  write32 (dword + 0x10, IO_APIC_ID << 24);
-  apicid_sb900 = IO_APIC_ID;
-  smp_write_ioapic(mc, apicid_sb900, 0x21, dword);
-
-  /* PIC IRQ routine */
-  for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
-    outb(byte, 0xC00);
-    outb(picr_data[byte], 0xC01);
-  }
-
-  /* APIC IRQ routine */
-  for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
-    outb(byte | 0x80, 0xC00);
-    outb(intr_data[byte], 0xC01);
-  }
-
-    /* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
+	struct mp_config_table *mc;
+	int bus_isa;
+	int boot_apic_id;
+	unsigned apic_version;
+	unsigned cpu_features;
+	unsigned cpu_feature_flags;
+	struct cpuid_result result;
+	unsigned long cpu_flag;
+
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+
+	mptable_init(mc, LOCAL_APIC_ADDR);
+	memcpy(mc->mpc_oem, "AMD     ", 8);
+
+	/*Inagua used dure core CPU with one die */
+	boot_apic_id = lapicid();
+	apic_version = lapic_read(LAPIC_LVR) & 0xff;
+	result = cpuid(1);
+	cpu_features = result.eax;
+	cpu_feature_flags = result.edx;
+	cpu_flag = MPC_CPU_ENABLED | MPC_CPU_BOOTPROCESSOR;
+	smp_write_processor(mc,
+	  0, apic_version,
+	  cpu_flag, cpu_features, cpu_feature_flags
+	);
+
+	cpu_flag = MPC_CPU_ENABLED;
+	smp_write_processor(mc,
+	  1, apic_version,
+	  cpu_flag, cpu_features, cpu_feature_flags
+	);
+
+	//mptable_write_buses(mc, NULL, &bus_isa);
+	my_smp_write_bus(mc, 0, "PCI   ");
+	my_smp_write_bus(mc, 1, "PCI   ");
+	bus_isa = 0x02;
+	my_smp_write_bus(mc, bus_isa, "ISA   ");
+
+	/* I/O APICs:   APIC ID Version State   Address */
+
+	u8 *dword;
+	u8 byte;
+
+	ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
+	dword = (u8 *)(((uintptr_t) dword) & 0xFFFFFFF0);
+	/* Set IO APIC ID onto IO_APIC_ID */
+	write32 (dword, 0x00);
+	write32 (dword + 0x10, IO_APIC_ID << 24);
+	apicid_sb900 = IO_APIC_ID;
+	smp_write_ioapic(mc, apicid_sb900, 0x21, dword);
+
+	/* PIC IRQ routine */
+	for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
+		outb(byte, 0xC00);
+		outb(picr_data[byte], 0xC01);
+	}
+
+	/* APIC IRQ routine */
+	for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
+		outb(byte | 0x80, 0xC00);
+		outb(intr_data[byte], 0xC01);
+	}
+
+	/* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
 #define IO_LOCAL_INT(type, intr, apicid, pin) \
-  smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
-  //mptable_add_isa_interrupts(mc, bus_isa, apicid_sb900, 0);
-  /*I/O Ints:          Type    Trigger             Polarity               Bus ID   IRQ  APIC ID       PIN# */
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x0, apicid_sb900, 0x0);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x1, apicid_sb900, 0x1);
-  smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x2, apicid_sb900, 0x2);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x3, apicid_sb900, 0x3);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x4, apicid_sb900, 0x4);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,  0, 0x49, apicid_sb900, 0x11);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x6, apicid_sb900, 0x6);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x7, apicid_sb900, 0x7);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x8, apicid_sb900, 0x8);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x9, apicid_sb900, 0x9);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,  bus_isa, 0xa, apicid_sb900, 0xa);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,  bus_isa, 0x1c, apicid_sb900, 0x13);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xc, apicid_sb900, 0xc);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xd, apicid_sb900, 0xd);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xe, apicid_sb900, 0xe);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xf, apicid_sb900, 0xf);
-
-  /* PCI interrupts are level triggered, and are
-   * associated with a specific bus/device/function tuple.
-   */
+	smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+
+	//mptable_add_isa_interrupts(mc, bus_isa, apicid_sb900, 0);
+	/*I/O Ints:          Type    Trigger             Polarity               Bus ID   IRQ  APIC ID       PIN# */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x0, apicid_sb900, 0x0);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x1, apicid_sb900, 0x1);
+	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x2, apicid_sb900, 0x2);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x3, apicid_sb900, 0x3);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x4, apicid_sb900, 0x4);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,  0, 0x49, apicid_sb900, 0x11);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x6, apicid_sb900, 0x6);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x7, apicid_sb900, 0x7);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x8, apicid_sb900, 0x8);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x9, apicid_sb900, 0x9);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,  bus_isa, 0xa, apicid_sb900, 0xa);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,  bus_isa, 0x1c, apicid_sb900, 0x13);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xc, apicid_sb900, 0xc);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xd, apicid_sb900, 0xd);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xe, apicid_sb900, 0xe);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xf, apicid_sb900, 0xf);
+
+	/* PCI interrupts are level triggered, and are
+	 * associated with a specific bus/device/function tuple.
+	 */
 #define PCI_INT(bus, dev, int_sign, pin) \
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb900, (pin))
-
-  /* Internal VGA */
-  PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
-  PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
-
-  /* SMBUS */
-  PCI_INT(0x0, 0x14, 0x0, 0x10);
-
-  /* HD Audio */
-  PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
-
-  /* USB */
-  PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
-  PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
-  PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
-  PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
-  PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
-  PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
-  PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
-
-  /* sata */
-  PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
-  PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
-
-
-  /* on board NIC & Slot PCIE.  */
-
-  /* PCI slots */
-  device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-  if (dev && dev->enabled) {
-	  u8 bus_pci = dev->link_list->secondary;
-
-	  /* PCI_SLOT 0. */
-	  PCI_INT(bus_pci, 0x5, 0x0, 0x14);
-	  PCI_INT(bus_pci, 0x5, 0x1, 0x15);
-	  PCI_INT(bus_pci, 0x5, 0x2, 0x16);
-	  PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
-	  /* PCI_SLOT 1. */
-	  PCI_INT(bus_pci, 0x6, 0x0, 0x15);
-	  PCI_INT(bus_pci, 0x6, 0x1, 0x16);
-	  PCI_INT(bus_pci, 0x6, 0x2, 0x17);
-	  PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
-	  /* PCI_SLOT 2. */
-	  PCI_INT(bus_pci, 0x7, 0x0, 0x16);
-	  PCI_INT(bus_pci, 0x7, 0x1, 0x17);
-	  PCI_INT(bus_pci, 0x7, 0x2, 0x14);
-	  PCI_INT(bus_pci, 0x7, 0x3, 0x15);
-  }
-
-  /* PCIe Lan*/
-  PCI_INT(0x0, 0x06, 0x0, 0x13);
-
-  /* FCH PCIe PortA */
-  PCI_INT(0x0, 0x15, 0x0, 0x10);
-  /* FCH PCIe PortB */
-  PCI_INT(0x0, 0x15, 0x1, 0x11);
-  /* FCH PCIe PortC */
-  PCI_INT(0x0, 0x15, 0x2, 0x12);
-  /* FCH PCIe PortD */
-  PCI_INT(0x0, 0x15, 0x3, 0x13);
-
-  /*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
-  IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
-  IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
-  /* There is no extension information... */
-
-  /* Compute the checksums */
-  return mptable_finalize(mc);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb900, (pin))
+
+	/* Internal VGA */
+	PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
+	PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+
+	/* SMBUS */
+	PCI_INT(0x0, 0x14, 0x0, 0x10);
+
+	/* HD Audio */
+	PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
+
+	/* USB */
+	PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
+	PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
+	PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
+	PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
+	PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
+	PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
+	PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
+
+	/* sata */
+	PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
+	PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+
+
+	/* on board NIC & Slot PCIE.  */
+
+	/* PCI slots */
+	device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+	if (dev && dev->enabled) {
+		u8 bus_pci = dev->link_list->secondary;
+
+		/* PCI_SLOT 0. */
+		PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+		PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+		PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+		PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+		/* PCI_SLOT 1. */
+		PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+		PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+		PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+		PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+		/* PCI_SLOT 2. */
+		PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+		PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+		PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+		PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+	}
+
+	/* PCIe Lan*/
+	PCI_INT(0x0, 0x06, 0x0, 0x13);
+
+	/* FCH PCIe PortA */
+	PCI_INT(0x0, 0x15, 0x0, 0x10);
+	/* FCH PCIe PortB */
+	PCI_INT(0x0, 0x15, 0x1, 0x11);
+	/* FCH PCIe PortC */
+	PCI_INT(0x0, 0x15, 0x2, 0x12);
+	/* FCH PCIe PortD */
+	PCI_INT(0x0, 0x15, 0x3, 0x13);
+
+	/*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
+	IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
+	IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
+	/* There is no extension information... */
+
+	/* Compute the checksums */
+	return mptable_finalize(mc);
 }

unsigned long write_smp_table(unsigned long addr)
 {
-  void *v;
-  v = smp_write_floating_table(addr, 0);
-  return (unsigned long)smp_write_config_table(v);
+	void *v;
+	v = smp_write_floating_table(addr, 0);
+	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c
index 7f8eba6..c24e42c 100644
--- a/src/mainboard/amd/union_station/mptable.c
+++ b/src/mainboard/amd/union_station/mptable.c
@@ -26,81 +26,81 @@

u8 intr_data[] = {
-  [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
-  [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
-  [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x10,0x11,0x12,0x13
+	[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
+	[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
+	[0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x10,0x11,0x12,0x13
 };

static void *smp_write_config_table(void *v)
 {
-  struct mp_config_table *mc;
-  int bus_isa;
+	struct mp_config_table *mc;
+	int bus_isa;

/*
     * By the time this function gets called, the IOAPIC registers
     * have been written so they can be read to get the correct
     * APIC ID and Version
     */
-  u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
-  u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
+	u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
+	u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);

-  mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);

-  mptable_init(mc, LOCAL_APIC_ADDR);
-  memcpy(mc->mpc_oem, "AMD     ", 8);
+	mptable_init(mc, LOCAL_APIC_ADDR);
+	memcpy(mc->mpc_oem, "AMD     ", 8);

-  smp_write_processors(mc);
+	smp_write_processors(mc);

-  mptable_write_buses(mc, NULL, &bus_isa);
+	mptable_write_buses(mc, NULL, &bus_isa);

-  /* I/O APICs:   APIC ID Version State   Address */
-  smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
+	/* I/O APICs:   APIC ID Version State   Address */
+	smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);

-  u8 byte;
+	u8 byte;

-  for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
-    outb(byte | 0x80, 0xC00);
-    outb(intr_data[byte], 0xC01);
-  }
+	for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
+		outb(byte | 0x80, 0xC00);
+		outb(intr_data[byte], 0xC01);
+	}

-  /* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
+	/* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
 #define IO_LOCAL_INT(type, intr, apicid, pin) \
-  smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+	smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));

-  mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
+	mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);

-  /* PCI interrupts are level triggered, and are
-   * associated with a specific bus/device/function tuple.
-   */
+	/* PCI interrupts are level triggered, and are
+	 * associated with a specific bus/device/function tuple.
+	 */
 #define PCI_INT(bus, dev, fn, pin) \
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))

-  /* APU Internal Graphic Device*/
-  PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
-  PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+	/* APU Internal Graphic Device*/
+	PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
+	PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);

-  //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
-  PCI_INT(0x0, 0x14, 0x0, 0x10);
-  /* Southbridge HD Audio: */
-  PCI_INT(0x0, 0x14, 0x2, 0x12);
+	//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
+	PCI_INT(0x0, 0x14, 0x0, 0x10);
+	/* Southbridge HD Audio: */
+	PCI_INT(0x0, 0x14, 0x2, 0x12);

-  PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
-  PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
-  PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
-  PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
-  PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
-  PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
+	PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
+	PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
+	PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
+	PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
+	PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
+	PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);

-  /* sata */
-  PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+	/* sata */
+	PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);

-  /* on board NIC & Slot PCIE.  */
+	/* on board NIC & Slot PCIE.  */

-  /* PCI slots */
+	/* PCI slots */
    device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
    if (dev && dev->enabled) {
    	u8 bus_pci = dev->link_list->secondary;
@@ -123,27 +123,27 @@ static void *smp_write_config_table(void *v)
    	PCI_INT(bus_pci, 0x7, 0x3, 0x15);
    }

-  /* PCIe PortA */
-  PCI_INT(0x0, 0x15, 0x0, 0x10);
-  /* PCIe PortB */
-  PCI_INT(0x0, 0x15, 0x1, 0x11);
-  /* PCIe PortC */
-  PCI_INT(0x0, 0x15, 0x2, 0x12);
-  /* PCIe PortD */
-  PCI_INT(0x0, 0x15, 0x3, 0x13);
-
-  /*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
-  IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
-  IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
-  /* There is no extension information... */
-
-  /* Compute the checksums */
-  return mptable_finalize(mc);
+	/* PCIe PortA */
+	PCI_INT(0x0, 0x15, 0x0, 0x10);
+	/* PCIe PortB */
+	PCI_INT(0x0, 0x15, 0x1, 0x11);
+	/* PCIe PortC */
+	PCI_INT(0x0, 0x15, 0x2, 0x12);
+	/* PCIe PortD */
+	PCI_INT(0x0, 0x15, 0x3, 0x13);
+
+	/*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
+	IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
+	IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
+	/* There is no extension information... */
+
+	/* Compute the checksums */
+	return mptable_finalize(mc);
 }

unsigned long write_smp_table(unsigned long addr)
 {
-  void *v;
-  v = smp_write_floating_table(addr, 0);
-  return (unsigned long)smp_write_config_table(v);
+	void *v;
+	v = smp_write_floating_table(addr, 0);
+	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/apple/macbook21/mptable.c b/src/mainboard/apple/macbook21/mptable.c
index e54d376..9bf168a 100644
--- a/src/mainboard/apple/macbook21/mptable.c
+++ b/src/mainboard/apple/macbook21/mptable.c
@@ -24,14 +24,14 @@

static void *smp_write_config_table(void *v)
 {
-        struct mp_config_table *mc;
+	struct mp_config_table *mc;
    int isa_bus;

-        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);

mptable_init(mc, LOCAL_APIC_ADDR);

-        smp_write_processors(mc);
+	smp_write_processors(mc);

mptable_write_buses(mc, NULL, &isa_bus);

diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c
index 1588964..eef3554 100644
--- a/src/mainboard/asrock/e350m1/mptable.c
+++ b/src/mainboard/asrock/e350m1/mptable.c
@@ -27,81 +27,81 @@

u8 intr_data[] = {
-  [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
-  [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
-  [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x10,0x11,0x12,0x13
+	[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
+	[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
+	[0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x10,0x11,0x12,0x13
 };

static void *smp_write_config_table(void *v)
 {
-  struct mp_config_table *mc;
-  int bus_isa;
+	struct mp_config_table *mc;
+	int bus_isa;

/*
     * By the time this function gets called, the IOAPIC registers
     * have been written so they can be read to get the correct
     * APIC ID and Version
     */
-  u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
-  u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
+	u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
+	u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);

-  mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);

-  mptable_init(mc, LOCAL_APIC_ADDR);
-  memcpy(mc->mpc_oem, "ASROCK  ", 8);
+	mptable_init(mc, LOCAL_APIC_ADDR);
+	memcpy(mc->mpc_oem, "ASROCK  ", 8);

-  smp_write_processors(mc);
+	smp_write_processors(mc);

-  mptable_write_buses(mc, NULL, &bus_isa);
+	mptable_write_buses(mc, NULL, &bus_isa);

-  /* I/O APICs:   APIC ID Version State   Address */
+	/* I/O APICs:   APIC ID Version State   Address */
    smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);

-  u8 byte;
+	u8 byte;

-  for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
-    outb(byte | 0x80, 0xC00);
-    outb(intr_data[byte], 0xC01);
-  }
+	for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
+		outb(byte | 0x80, 0xC00);
+		outb(intr_data[byte], 0xC01);
+	}

-  /* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
+	/* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
 #define IO_LOCAL_INT(type, intr, apicid, pin) \
-  smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+	smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));

-  mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
+	mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);

-  /* PCI interrupts are level triggered, and are
-   * associated with a specific bus/device/function tuple.
-   */
+	/* PCI interrupts are level triggered, and are
+	 * associated with a specific bus/device/function tuple.
+	 */
 #define PCI_INT(bus, dev, fn, pin) \
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))

-  /* APU Internal Graphic Device*/
-  PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
-  PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+	/* APU Internal Graphic Device*/
+	PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
+	PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);

-  //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
-  PCI_INT(0x0, 0x14, 0x0, 0x10);
-  /* Southbridge HD Audio: */
-  PCI_INT(0x0, 0x14, 0x2, 0x12);
+	//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
+	PCI_INT(0x0, 0x14, 0x0, 0x10);
+	/* Southbridge HD Audio: */
+	PCI_INT(0x0, 0x14, 0x2, 0x12);

-  PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
-  PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
-  PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
-  PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
-  PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
-  PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
+	PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
+	PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
+	PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
+	PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
+	PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
+	PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);

-  /* sata */
-  PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+	/* sata */
+	PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);

-  /* on board NIC & Slot PCIE.  */
+	/* on board NIC & Slot PCIE.  */

-  /* PCI slots */
+	/* PCI slots */
    device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
    if (dev && dev->enabled) {
    	u8 bus_pci = dev->link_list->secondary;
@@ -124,27 +124,27 @@ static void *smp_write_config_table(void *v)
    	PCI_INT(bus_pci, 0x7, 0x3, 0x15);
    }

-  /* PCIe PortA */
-  PCI_INT(0x0, 0x15, 0x0, 0x10);
-  /* PCIe PortB */
-  PCI_INT(0x0, 0x15, 0x1, 0x11);
-  /* PCIe PortC */
-  PCI_INT(0x0, 0x15, 0x2, 0x12);
-  /* PCIe PortD */
-  PCI_INT(0x0, 0x15, 0x3, 0x13);
-
-  /*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
-  IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
-  IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
-  /* There is no extension information... */
-
-  /* Compute the checksums */
-  return mptable_finalize(mc);
+	/* PCIe PortA */
+	PCI_INT(0x0, 0x15, 0x0, 0x10);
+	/* PCIe PortB */
+	PCI_INT(0x0, 0x15, 0x1, 0x11);
+	/* PCIe PortC */
+	PCI_INT(0x0, 0x15, 0x2, 0x12);
+	/* PCIe PortD */
+	PCI_INT(0x0, 0x15, 0x3, 0x13);
+
+	/*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
+	IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
+	IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
+	/* There is no extension information... */
+
+	/* Compute the checksums */
+	return mptable_finalize(mc);
 }

unsigned long write_smp_table(unsigned long addr)
 {
-  void *v;
-  v = smp_write_floating_table(addr, 0);
-  return (unsigned long)smp_write_config_table(v);
+	void *v;
+	v = smp_write_floating_table(addr, 0);
+	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/asrock/imb-a180/mptable.c b/src/mainboard/asrock/imb-a180/mptable.c
index 2fc380f..6241282 100644
--- a/src/mainboard/asrock/imb-a180/mptable.c
+++ b/src/mainboard/asrock/imb-a180/mptable.c
@@ -151,7 +151,7 @@ static void *smp_write_config_table(void *v)
     * associated with a specific bus/device/function tuple.
     */
 #define PCI_INT(bus, dev, int_sign, pin)				\
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))

/* Internal VGA */
    PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/asus/f2a85-m/mptable.c b/src/mainboard/asus/f2a85-m/mptable.c
index 4f00dad..09d9455 100644
--- a/src/mainboard/asus/f2a85-m/mptable.c
+++ b/src/mainboard/asus/f2a85-m/mptable.c
@@ -111,7 +111,7 @@ static void *smp_write_config_table(void *v)
     * associated with a specific bus/device/function tuple.
     */
 #define PCI_INT(bus, dev, int_sign, pin)				\
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))

/* IOMMU */
    PCI_INT(0x0, 0x0, 0x0, 0x10);
diff --git a/src/mainboard/bap/ode_e21XX/mptable.c b/src/mainboard/bap/ode_e21XX/mptable.c
index a2ba7f4..925526c 100644
--- a/src/mainboard/bap/ode_e21XX/mptable.c
+++ b/src/mainboard/bap/ode_e21XX/mptable.c
@@ -111,7 +111,7 @@ static void *smp_write_config_table(void *v)
     * associated with a specific bus/device/function tuple.
     */
 #define PCI_INT(bus, dev, int_sign, pin)				\
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))

/* Internal VGA */
    PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/broadcom/blast/mptable.c b/src/mainboard/broadcom/blast/mptable.c
index 2ecc6af..81c3049 100644
--- a/src/mainboard/broadcom/blast/mptable.c
+++ b/src/mainboard/broadcom/blast/mptable.c
@@ -9,43 +9,43 @@
 #endif
 #include <cpu/amd/amdk8_sysconf.h>

-extern  unsigned char bus_bcm5780[7];
-extern  unsigned char bus_bcm5785_0;
-extern  unsigned char bus_bcm5785_1;
-extern  unsigned char bus_bcm5785_1_1;
-extern  unsigned apicid_bcm5785[3];
+extern unsigned char bus_bcm5780[7];
+extern unsigned char bus_bcm5785_0;
+extern unsigned char bus_bcm5785_1;
+extern unsigned char bus_bcm5785_1_1;
+extern unsigned apicid_bcm5785[3];

-extern  unsigned sbdn2;
+extern unsigned sbdn2;

static void *smp_write_config_table(void *v)
 {
-        struct mp_config_table *mc;
+	struct mp_config_table *mc;
    int i, bus_isa;

-        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);

mptable_init(mc, LOCAL_APIC_ADDR);

-        smp_write_processors(mc);
+	smp_write_processors(mc);

get_bus_conf();

mptable_write_buses(mc, NULL, &bus_isa);

/*I/O APICs:	APIC ID	Version	State		Address*/
-        {
-                device_t dev = 0;
+	{
+		device_t dev = 0;
    	struct resource *res;
    	for(i = 0; i < 3; i++) {
-	                dev = dev_find_device(0x1166, 0x0235, dev);
-        	        if (dev) {
+			dev = dev_find_device(0x1166, 0x0235, dev);
+			if (dev) {
    			res = find_resource(dev, PCI_BASE_ADDRESS_0);
    			if (res) {
    				smp_write_ioapic(mc, apicid_bcm5785[i],
    						 0x11,
    						 res2mmio(res, 0, 0));
    			}
-        	        }
+			}
    	}

}
@@ -59,77 +59,77 @@ static void *smp_write_config_table(void *v)

//SATA
    outb(0x07, 0xc00); outb(0x0f, 0xc01);
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_1, (0x0e << 2)|0, apicid_bcm5785[0], 0xf);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_1, (0x0e << 2)|0, apicid_bcm5785[0], 0xf);

//USB
    outb(0x01, 0xc00); outb(0x0a, 0xc01);
-        for(i = 0; i < 3; i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, ((2+sysconf.sbdn)<<2)|i, apicid_bcm5785[0], 0xa); //
-        }
+	for(i = 0; i < 3; i++) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, ((2+sysconf.sbdn)<<2)|i, apicid_bcm5785[0], 0xa); //
+	}

-        /* enable int */
-        /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/
-        {
-                device_t dev;
-                dev = dev_find_device(0x1166, 0x0205, 0);
-                if(dev) {
-                        uint32_t dword;
-                        dword = pci_read_config32(dev, 0x6c);
-                        dword |= (1 << 4); // enable interrupts
-                        pci_write_config32(dev, 0x6c, dword);
+	/* enable int */
+	/* why here? must get the BAR and PCI command bit 1 set before enable it ....*/
+	{
+		device_t dev;
+		dev = dev_find_device(0x1166, 0x0205, 0);
+		if(dev) {
+			uint32_t dword;
+			dword = pci_read_config32(dev, 0x6c);
+			dword |= (1 << 4); // enable interrupts
+			pci_write_config32(dev, 0x6c, dword);

-                }
+		}

-        }
+	}

//First pci-x slot (on bcm5785) under bus_bcm5785_1:d.0
-        for(i = 0; i < 4; i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_1_1, (4 << 2)|i, apicid_bcm5785[1], 2 + (0+i)%4); //
-        }
+	for(i = 0; i < 4; i++) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_1_1, (4 << 2)|i, apicid_bcm5785[1], 2 + (0+i)%4); //
+	}

//pci slot (on bcm5785)
-        for(i = 0; i < 4; i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, (4 << 2)|i, apicid_bcm5785[1], i%2); //
-        }
+	for(i = 0; i < 4; i++) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, (4 << 2)|i, apicid_bcm5785[1], i%2); //
+	}

//onboard ati
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, (5 << 2)|0, apicid_bcm5785[1], 0x1);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, (5 << 2)|0, apicid_bcm5785[1], 0x1);

//PCI-X on bcm5780
-        for(i = 0; i < 4; i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[1], (4 << 2)|i, apicid_bcm5785[1], 6 + (0+i)%4); //
-        }
+	for(i = 0; i < 4; i++) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[1], (4 << 2)|i, apicid_bcm5785[1], 6 + (0+i)%4); //
+	}

-        for(i = 0; i < 4; i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[1], (5 << 2)|i, apicid_bcm5785[1], 6 + (1+i)%4); //
-        }
+	for(i = 0; i < 4; i++) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[1], (5 << 2)|i, apicid_bcm5785[1], 6 + (1+i)%4); //
+	}

//onboard Broadcom
-        for(i = 0; i < 2; i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[2], (4 << 2)|i, apicid_bcm5785[1], 0xa + (0+i)%4); //
-        }
+	for(i = 0; i < 2; i++) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[2], (4 << 2)|i, apicid_bcm5785[1], 0xa + (0+i)%4); //
+	}

// First PCI-E x8
-        for(i = 0; i < 4; i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[5], (0 << 2)|i, apicid_bcm5785[1], 0xe); //
-        }
+	for(i = 0; i < 4; i++) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[5], (0 << 2)|i, apicid_bcm5785[1], 0xe); //
+	}

// Second PCI-E x8
-        for(i = 0; i < 4; i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[3], (0 << 2)|i, apicid_bcm5785[1], 0xc); //
-        }
+	for(i = 0; i < 4; i++) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[3], (0 << 2)|i, apicid_bcm5785[1], 0xc); //
+	}

// Third PCI-E x1
-        for(i = 0; i < 4; i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[4], (0 << 2)|i, apicid_bcm5785[1], 0xd); //
-        }
+	for(i = 0; i < 4; i++) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[4], (0 << 2)|i, apicid_bcm5785[1], 0xd); //
+	}

/*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
    mptable_lintsrc(mc, bus_isa);
diff --git a/src/mainboard/getac/p470/mptable.c b/src/mainboard/getac/p470/mptable.c
index 8e792b7..a9e8a26 100644
--- a/src/mainboard/getac/p470/mptable.c
+++ b/src/mainboard/getac/p470/mptable.c
@@ -24,14 +24,14 @@

static void *smp_write_config_table(void *v)
 {
-        struct mp_config_table *mc;
+	struct mp_config_table *mc;
    int isa_bus;

-        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);

mptable_init(mc, LOCAL_APIC_ADDR);

-        smp_write_processors(mc);
+	smp_write_processors(mc);

mptable_write_buses(mc, NULL, &isa_bus);

diff --git a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
index a7962f54..1544205 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
@@ -30,15 +30,15 @@ extern unsigned apicid_sis966;

static void *smp_write_config_table(void *v)
 {
-        struct mp_config_table *mc;
+	struct mp_config_table *mc;
    unsigned sbdn;
    int i, j, bus_isa;

-        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);

mptable_init(mc, LOCAL_APIC_ADDR);

-        smp_write_processors(mc);
+	smp_write_processors(mc);

get_bus_conf();
    sbdn = sysconf.sbdn;
@@ -46,13 +46,13 @@ static void *smp_write_config_table(void *v)
    mptable_write_buses(mc, NULL, &bus_isa);

/*I/O APICs:	APIC ID	Version	State		Address*/
-        {
-                device_t dev;
+	{
+		device_t dev;
    	struct resource *res;
    	uint32_t dword;

-                dev = dev_find_slot(bus_sis966[0], PCI_DEVFN(sbdn+ 0x1,0));
-                if (dev) {
+		dev = dev_find_slot(bus_sis966[0], PCI_DEVFN(sbdn+ 0x1,0));
+		if (dev) {
    		res = find_resource(dev, PCI_BASE_ADDRESS_1);
    		if (res) {
    			smp_write_ioapic(mc, apicid_sis966, 0x11,
@@ -60,15 +60,15 @@ static void *smp_write_config_table(void *v)
    		}

dword = 0x43c6c643;
-	        	pci_write_config32(dev, 0x7c, dword);
+			pci_write_config32(dev, 0x7c, dword);

-		        dword = 0x81001a00;
-		        pci_write_config32(dev, 0x80, dword);
+			dword = 0x81001a00;
+			pci_write_config32(dev, 0x80, dword);

-	        	dword = 0xd0001202;
-		        pci_write_config32(dev, 0x84, dword);
+			dword = 0xd0001202;
+			pci_write_config32(dev, 0x84, dword);

-                }
+		}
    }

mptable_add_isa_interrupts(mc, bus_isa, apicid_sis966, 0);
@@ -77,28 +77,28 @@ static void *smp_write_config_table(void *v)
  * associated with a specific bus/device/function tuple.
  */
 #define PCI_INT(bus, dev, fn, pin)					\
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sis966[bus], (((dev)<<2)|(fn)), apicid_sis966, (pin))
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sis966[bus], (((dev)<<2)|(fn)), apicid_sis966, (pin))

-        PCI_INT(0, sbdn+1, 1, 0xa);
-        PCI_INT(0, sbdn+2, 0, 0x16); // 22
-        PCI_INT(0, sbdn+2, 1, 0x17); // 23
-        PCI_INT(0, sbdn+6, 1, 0x17); // 23
-        PCI_INT(0, sbdn+5, 0, 0x14); // 20
-        PCI_INT(0, sbdn+5, 1, 0x17); // 23
-        PCI_INT(0, sbdn+5, 2, 0x15); // 21
-        PCI_INT(0, sbdn+8, 0, 0x16); // 22
+	PCI_INT(0, sbdn+1, 1, 0xa);
+	PCI_INT(0, sbdn+2, 0, 0x16); // 22
+	PCI_INT(0, sbdn+2, 1, 0x17); // 23
+	PCI_INT(0, sbdn+6, 1, 0x17); // 23
+	PCI_INT(0, sbdn+5, 0, 0x14); // 20
+	PCI_INT(0, sbdn+5, 1, 0x17); // 23
+	PCI_INT(0, sbdn+5, 2, 0x15); // 21
+	PCI_INT(0, sbdn+8, 0, 0x16); // 22

for(j = 7; j >= 2; j--) {
    	if(!bus_sis966[j]) continue;
-	        for(i = 0; i < 4; i++) {
-        	        PCI_INT(j, 0x00, i, 0x10 + (2+j+i+4-sbdn%4)%4);
-        	}
+		for(i = 0; i < 4; i++) {
+			PCI_INT(j, 0x00, i, 0x10 + (2+j+i+4-sbdn%4)%4);
+		}
    }

for(j = 0; j < 2; j++)
-	        for(i = 0; i < 4; i++) {
-        	        PCI_INT(1, 0x06+j, i, 0x10 + (2+i+j)%4);
-	        }
+		for(i = 0; i < 4; i++) {
+			PCI_INT(1, 0x06+j, i, 0x10 + (2+i+j)%4);
+		}

/*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
    mptable_lintsrc(mc, bus_isa);
diff --git a/src/mainboard/gigabyte/m57sli/mptable.c b/src/mainboard/gigabyte/m57sli/mptable.c
index 403b969..019a7f5 100644
--- a/src/mainboard/gigabyte/m57sli/mptable.c
+++ b/src/mainboard/gigabyte/m57sli/mptable.c
@@ -29,15 +29,15 @@ extern unsigned apicid_mcp55;

static void *smp_write_config_table(void *v)
 {
-        struct mp_config_table *mc;
+	struct mp_config_table *mc;
    unsigned sbdn;
    int i, j, k, bus_isa;

-        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);

mptable_init(mc, LOCAL_APIC_ADDR);

-        smp_write_processors(mc);
+	smp_write_processors(mc);

get_bus_conf();
    sbdn = sysconf.sbdn;
@@ -45,22 +45,22 @@ static void *smp_write_config_table(void *v)
    mptable_write_buses(mc, NULL, &bus_isa);

/*I/O APICs:	APIC ID	Version	State		Address*/
-        {
-                device_t dev;
+	{
+		device_t dev;
    	struct resource *res;

-                dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
-                if (dev) {
+		dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
+		if (dev) {
    		res = find_resource(dev, PCI_BASE_ADDRESS_1);
    		if (res) {
    			smp_write_ioapic(mc, apicid_mcp55, 0x11,
    					 res2mmio(res, 0, 0));
    		}
    		/* set up the interrupt registers of mcp55 */
-	        	pci_write_config32(dev, 0x7c, 0xc643c643);
-		        pci_write_config32(dev, 0x80, 0x8da01009);
-		        pci_write_config32(dev, 0x84, 0x200018d2);
-                }
+			pci_write_config32(dev, 0x7c, 0xc643c643);
+			pci_write_config32(dev, 0x80, 0x8da01009);
+			pci_write_config32(dev, 0x84, 0x200018d2);
+		}
    }

mptable_add_isa_interrupts(mc, bus_isa, apicid_mcp55, 0);
@@ -83,28 +83,28 @@ static void *smp_write_config_table(void *v)
    PCI_INT(0,sbdn+8,0, 20); /* GBit Ethernet */

/* The PCIe slots, each on its own bus */
-        k = 1;
-        for(i = 0; i < 4; i++){
-                for(j = 7; j > 1; j--){
-                        if(k > 3) k = 0;
-                        PCI_INT(j,0,i, 16+k);
-                        k++;
-                }
-                k--;
-        }
+	k = 1;
+	for(i = 0; i < 4; i++){
+		for(j = 7; j > 1; j--){
+			if(k > 3) k = 0;
+			PCI_INT(j,0,i, 16+k);
+			k++;
+		}
+		k--;
+	}

/* On bus 1: the PCI bus slots...
-	   physical PCI slots are j = 7,8
-	   FireWire is j = 10
+	 * physical PCI slots are j = 7,8
+	 * FireWire is j = 10
    */
-        k = 2;
-        for(i = 0; i < 4; i++){
-                for(j = 6; j < 11; j++){
-                        if(k > 3) k = 0;
-                        PCI_INT(1,j,i, 16+k);
-                        k++;
-                }
-        }
+	k = 2;
+	for(i = 0; i < 4; i++){
+		for(j = 6; j < 11; j++){
+			if(k > 3) k = 0;
+			PCI_INT(1,j,i, 16+k);
+			k++;
+		}
+	}

/*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
    mptable_lintsrc(mc, bus_isa);
diff --git a/src/mainboard/hp/abm/mptable.c b/src/mainboard/hp/abm/mptable.c
index 2fc380f..6241282 100644
--- a/src/mainboard/hp/abm/mptable.c
+++ b/src/mainboard/hp/abm/mptable.c
@@ -151,7 +151,7 @@ static void *smp_write_config_table(void *v)
     * associated with a specific bus/device/function tuple.
     */
 #define PCI_INT(bus, dev, int_sign, pin)				\
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))

/* Internal VGA */
    PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c
index f1cc663..9e63caf 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c
@@ -112,7 +112,7 @@ static void *smp_write_config_table(void *v)
     * associated with a specific bus/device/function tuple.
     */
 #define PCI_INT(bus, dev, int_sign, pin)				\
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))

/* IOMMU */
    PCI_INT(0x0, 0x00, 0x0, 0x10);
diff --git a/src/mainboard/ibase/mb899/mptable.c b/src/mainboard/ibase/mb899/mptable.c
index bbdf0bf..89fba6b 100644
--- a/src/mainboard/ibase/mb899/mptable.c
+++ b/src/mainboard/ibase/mb899/mptable.c
@@ -23,16 +23,16 @@

static void *smp_write_config_table(void *v)
 {
-        struct mp_config_table *mc;
+	struct mp_config_table *mc;
    struct device *riser = NULL, *firewire = NULL;
    int firewire_bus = 0, riser_bus = 0, isa_bus;
    int ioapic_id;

-        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);

mptable_init(mc, LOCAL_APIC_ADDR);

-        smp_write_processors(mc);
+	smp_write_processors(mc);

firewire = dev_find_device(0x104c, 0x8023, 0);
    if (firewire) {
diff --git a/src/mainboard/intel/d945gclf/mptable.c b/src/mainboard/intel/d945gclf/mptable.c
index 593c098..342f1e6 100644
--- a/src/mainboard/intel/d945gclf/mptable.c
+++ b/src/mainboard/intel/d945gclf/mptable.c
@@ -23,14 +23,14 @@

static void *smp_write_config_table(void *v)
 {
-        struct mp_config_table *mc;
+	struct mp_config_table *mc;
    int isa_bus;

-        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);

mptable_init(mc, LOCAL_APIC_ADDR);

-        smp_write_processors(mc);
+	smp_write_processors(mc);

mptable_write_buses(mc, NULL, &isa_bus);

diff --git a/src/mainboard/intel/eagleheights/mptable.c b/src/mainboard/intel/eagleheights/mptable.c
index ae05bb9..dae3879 100644
--- a/src/mainboard/intel/eagleheights/mptable.c
+++ b/src/mainboard/intel/eagleheights/mptable.c
@@ -55,7 +55,7 @@

static void *smp_write_config_table(void *v)
 {
-        struct mp_config_table *mc;
+	struct mp_config_table *mc;
    unsigned char bus_chipset, bus_pci;
    unsigned char bus_pcie_a, bus_pcie_a1, bus_pcie_b;
    int bus_isa, i;
@@ -67,15 +67,15 @@ static void *smp_write_config_table(void *v)
    dev = dev_find_slot(0, PCI_DEVFN(0x1F,0));
    res = find_resource(dev, RCBA);
    if (!res) {
-	  return NULL;
+		return NULL;
    }
    rcba = res2mmio(res, 0, 0);

-        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);

mptable_init(mc, LOCAL_APIC_ADDR);

-        smp_write_processors(mc);
+	smp_write_processors(mc);

/* Get bus numbers */
    bus_chipset = 0;
@@ -83,34 +83,34 @@ static void *smp_write_config_table(void *v)
    /* PCI */
    dev = dev_find_slot(0, PCI_DEVFN(0x1E,0));
    if (dev) {
-	  bus_pci = pci_read_config8(dev, PCI_SECONDARY_BUS);
+		bus_pci = pci_read_config8(dev, PCI_SECONDARY_BUS);
    } else {
-	  printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");
-	  bus_pci = 6;
+		printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");
+		bus_pci = 6;
    }

dev = dev_find_slot(0, PCI_DEVFN(2,0));
    if(dev) {
-	  bus_pcie_a = pci_read_config8(dev, PCI_SECONDARY_BUS);
+		bus_pcie_a = pci_read_config8(dev, PCI_SECONDARY_BUS);
    } else {
-	  printk(BIOS_DEBUG, "ERROR - could not find PCIe Port A  0:2.0, using defaults\n");
-	  bus_pcie_a = 1;
+		printk(BIOS_DEBUG, "ERROR - could not find PCIe Port A  0:2.0, using defaults\n");
+		bus_pcie_a = 1;
    }

dev = dev_find_slot(0, PCI_DEVFN(3,0));
    if(dev) {
-	  bus_pcie_a1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+		bus_pcie_a1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
    } else {
-	  printk(BIOS_DEBUG, "ERROR - could not find PCIe Port B 0:3.0, using defaults\n");
-	  bus_pcie_a1 = 2;
+		printk(BIOS_DEBUG, "ERROR - could not find PCIe Port B 0:3.0, using defaults\n");
+		bus_pcie_a1 = 2;
    }

dev = dev_find_slot(0, PCI_DEVFN(0x1C,0));
    if(dev) {
-	  bus_pcie_b = pci_read_config8(dev, PCI_SECONDARY_BUS);
+		bus_pcie_b = pci_read_config8(dev, PCI_SECONDARY_BUS);
    } else {
-	  printk(BIOS_DEBUG, "ERROR - could not find PCIe Port B 0:3.0, using defaults\n");
-	  bus_pcie_b = 3;
+		printk(BIOS_DEBUG, "ERROR - could not find PCIe Port B 0:3.0, using defaults\n");
+		bus_pcie_b = 3;
    }

mptable_write_buses(mc, NULL, &bus_isa);
@@ -140,45 +140,45 @@ static void *smp_write_config_table(void *v)
    /* PCIe Port B
     */
    for(i = 0; i < 4; i++) {
-	  pin = (read32(rcba + RCBA_D28IP) >> (i * 4)) & 0x0F;
-	  if(pin > 0) {
-	    pin -= 1;
-	    route = PIRQ_A + ((read16(rcba + RCBA_D28IR) >> (pin * 4)) & 0x07);
-	    smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(28, pin), IO_APIC0, route);
-	  }
+		pin = (read32(rcba + RCBA_D28IP) >> (i * 4)) & 0x0F;
+		if(pin > 0) {
+			pin -= 1;
+			route = PIRQ_A + ((read16(rcba + RCBA_D28IR) >> (pin * 4)) & 0x07);
+			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(28, pin), IO_APIC0, route);
+		}
    }

/* USB 1.1 : device 29, function 0, 1
     */
    for(i = 0; i < 2; i++) {
-	  pin = (read32(rcba + RCBA_D29IP) >> (i * 4)) & 0x0F;
-	  if(pin > 0) {
-	    pin -= 1;
-	    route = PIRQ_A + ((read16(rcba + RCBA_D29IR) >> (pin * 4)) & 0x07);
-	    smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(29, pin), IO_APIC0, route);
-	  }
+		pin = (read32(rcba + RCBA_D29IP) >> (i * 4)) & 0x0F;
+		if(pin > 0) {
+			 pin -= 1;
+			route = PIRQ_A + ((read16(rcba + RCBA_D29IR) >> (pin * 4)) & 0x07);
+			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(29, pin), IO_APIC0, route);
+		}
    }

/* USB 2.0 : device 29, function 7
    */
    pin = (read32(rcba + RCBA_D29IP) >> (7 * 4)) & 0x0F;
    if(pin > 0) {
-	  pin -= 1;
-	  route = PIRQ_A + ((read16(rcba + RCBA_D29IR) >> (pin * 4)) & 0x07);
-	  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(29, pin), IO_APIC0, route);
+		pin -= 1;
+		route = PIRQ_A + ((read16(rcba + RCBA_D29IR) >> (pin * 4)) & 0x07);
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(29, pin), IO_APIC0, route);
    }

/* SATA : device 31 function 2
-	   SMBus : device 31 function 3
-	   Performance counters : device 31 function 4
+	 * SMBus : device 31 function 3
+	 * Performance counters : device 31 function 4
     */
    for(i = 2; i < 5; i++) {
-	  pin = (read32(rcba + RCBA_D31IP) >> (i * 4)) & 0x0F;
-	  if(pin > 0) {
-	    pin -= 1;
-	    route = PIRQ_A + ((read16(rcba + RCBA_D31IR) >> (pin * 4)) & 0x07);
-	    smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(31, pin), IO_APIC0, route);
-	  }
+		pin = (read32(rcba + RCBA_D31IP) >> (i * 4)) & 0x0F;
+		if(pin > 0) {
+			pin -= 1;
+			route = PIRQ_A + ((read16(rcba + RCBA_D31IR) >> (pin * 4)) & 0x07);
+			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(31, pin), IO_APIC0, route);
+		}
    }

/* SLOTS */
diff --git a/src/mainboard/kontron/986lcd-m/mptable.c b/src/mainboard/kontron/986lcd-m/mptable.c
index 858a7ef..2ee2890 100644
--- a/src/mainboard/kontron/986lcd-m/mptable.c
+++ b/src/mainboard/kontron/986lcd-m/mptable.c
@@ -23,16 +23,16 @@

static void *smp_write_config_table(void *v)
 {
-        struct mp_config_table *mc;
+	struct mp_config_table *mc;
    struct device *riser = NULL, *firewire = NULL;
    int firewire_bus = 0, riser_bus = 0, isa_bus;
    int ioapic_id;

-        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);

mptable_init(mc, LOCAL_APIC_ADDR);

-        smp_write_processors(mc);
+	smp_write_processors(mc);

firewire = dev_find_device(0x104c, 0x8023, 0);
    if (firewire) {
diff --git a/src/mainboard/lenovo/g505s/mptable.c b/src/mainboard/lenovo/g505s/mptable.c
index f1cc663..9e63caf 100644
--- a/src/mainboard/lenovo/g505s/mptable.c
+++ b/src/mainboard/lenovo/g505s/mptable.c
@@ -112,7 +112,7 @@ static void *smp_write_config_table(void *v)
     * associated with a specific bus/device/function tuple.
     */
 #define PCI_INT(bus, dev, int_sign, pin)				\
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))

/* IOMMU */
    PCI_INT(0x0, 0x00, 0x0, 0x10);
diff --git a/src/mainboard/lenovo/t60/mptable.c b/src/mainboard/lenovo/t60/mptable.c
index ebdafda..d798d8d 100644
--- a/src/mainboard/lenovo/t60/mptable.c
+++ b/src/mainboard/lenovo/t60/mptable.c
@@ -24,14 +24,14 @@

static void *smp_write_config_table(void *v)
 {
-        struct mp_config_table *mc;
+	struct mp_config_table *mc;
    int isa_bus;

-        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);

mptable_init(mc, LOCAL_APIC_ADDR);

-        smp_write_processors(mc);
+	smp_write_processors(mc);

mptable_write_buses(mc, NULL, &isa_bus);

diff --git a/src/mainboard/lenovo/x60/mptable.c b/src/mainboard/lenovo/x60/mptable.c
index 5e3de67..a800742 100644
--- a/src/mainboard/lenovo/x60/mptable.c
+++ b/src/mainboard/lenovo/x60/mptable.c
@@ -24,14 +24,14 @@

static void *smp_write_config_table(void *v)
 {
-        struct mp_config_table *mc;
+	struct mp_config_table *mc;
    int isa_bus;

-        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);

mptable_init(mc, LOCAL_APIC_ADDR);

-        smp_write_processors(mc);
+	smp_write_processors(mc);

mptable_write_buses(mc, NULL, &isa_bus);

diff --git a/src/mainboard/msi/ms9185/mptable.c b/src/mainboard/msi/ms9185/mptable.c
index fccb200..38cc72b 100644
--- a/src/mainboard/msi/ms9185/mptable.c
+++ b/src/mainboard/msi/ms9185/mptable.c
@@ -34,16 +34,16 @@

static void *smp_write_config_table(void *v)
 {
-        struct mp_config_table *mc;
+	struct mp_config_table *mc;

int i, bus_isa;
    struct mb_sysconf_t *m;

-        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);

mptable_init(mc, LOCAL_APIC_ADDR);

-        smp_write_processors(mc);
+	smp_write_processors(mc);

get_bus_conf();
    m = sysconf.mb;
@@ -51,108 +51,108 @@ static void *smp_write_config_table(void *v)
    mptable_write_buses(mc, NULL, &bus_isa);

/*I/O APICs:   APIC ID Version State           Address*/
-        {
+	{
    	device_t dev = 0;
-               struct resource *res;
-               for(i = 0; i < 3; i++) {
-                       dev = dev_find_device(0x1166, 0x0235, dev);
-                       if (dev) {
-                               res = find_resource(dev, PCI_BASE_ADDRESS_0);
-                               if (res) {
-                                       smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11,
-                                                        res2mmio(res, 0, 0));
-                               }
-                       }
-               }
-
-       }
+		struct resource *res;
+		for(i = 0; i < 3; i++) {
+			dev = dev_find_device(0x1166, 0x0235, dev);
+			if (dev) {
+				res = find_resource(dev, PCI_BASE_ADDRESS_0);
+				if (res) {
+					smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11,
+							res2mmio(res, 0, 0));
+				}
+			}
+		}
+
+	}

mptable_add_isa_interrupts(mc, bus_isa, m->apicid_bcm5785[0], 0);

//IDE
-       outb(0x02, 0xc00); outb(0x0e, 0xc01);
+	outb(0x02, 0xc00); outb(0x0e, 0xc01);

-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, m->apicid_bcm5785[0], 0xe); // IDE
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, m->apicid_bcm5785[0], 0xe); // IDE

//SATA
-       outb(0x07, 0xc00); outb(0x0f, 0xc01);
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e << 2)|0, m->apicid_bcm5785[0], 0xf);
+	outb(0x07, 0xc00); outb(0x0f, 0xc01);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e << 2)|0, m->apicid_bcm5785[0], 0xf);

//USB
-       outb(0x01, 0xc00); outb(0x0a, 0xc01);
-        for(i = 0; i < 3; i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, ((2+sysconf.sbdn)<<2)|i, m->apicid_bcm5785[0], 0xa); //
-        }
-
-
-
-        /* enable int */
-        /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/
-        {
-                device_t dev;
-                dev = dev_find_device(0x1166, 0x0205, 0);
-                if(dev) {
-                        uint32_t dword;
-                        dword = pci_read_config32(dev, 0x6c);
-                        dword |= (1 << 4); // enable interrupts
-                        pci_write_config32(dev, 0x6c, dword);
-                }
-                }
+	outb(0x01, 0xc00); outb(0x0a, 0xc01);
+	for(i = 0; i < 3; i++) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, ((2+sysconf.sbdn)<<2)|i, m->apicid_bcm5785[0], 0xa); //
+	}
+
+
+
+	/* enable int */
+	/* why here? must get the BAR and PCI command bit 1 set before enable it ....*/
+	{
+		device_t dev;
+		dev = dev_find_device(0x1166, 0x0205, 0);
+		if(dev) {
+			uint32_t dword;
+			dword = pci_read_config32(dev, 0x6c);
+			dword |= (1 << 4); // enable interrupts
+			pci_write_config32(dev, 0x6c, dword);
+		}
+		}

//First pci-x slot (on bcm5785) under bus_bcm5785_1:d.0
-       // AIC 8130 Galileo Technology...
-        for(i = 0; i < 4; i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (6 << 2)|i, m->apicid_bcm5785[1], 2 + (1+i)%4); //
-        }
+	// AIC 8130 Galileo Technology...
+	for(i = 0; i < 4; i++) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (6 << 2)|i, m->apicid_bcm5785[1], 2 + (1+i)%4); //
+	}

//pci slot (on bcm5785)
-        for(i = 0; i < 4; i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (5 << 2)|i, m->apicid_bcm5785[1], 8+i%4); //
-        }
+	for(i = 0; i < 4; i++) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (5 << 2)|i, m->apicid_bcm5785[1], 8+i%4); //
+	}

//onboard ati
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (4 << 2)|0, m->apicid_bcm5785[1], 0x1);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (4 << 2)|0, m->apicid_bcm5785[1], 0x1);

//PCI-X on bcm5780
-        for(i = 0; i < 4; i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[1], (4 << 2)|i, m->apicid_bcm5785[1], 2 + (0+i)%4); //
-        }
+	for(i = 0; i < 4; i++) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[1], (4 << 2)|i, m->apicid_bcm5785[1], 2 + (0+i)%4); //
+	}

//onboard Broadcom
-        for(i = 0; i < 2; i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[2], (4 << 2)|i, m->apicid_bcm5785[1], 0xa + (0+i)%4); //
-        }
+	for(i = 0; i < 2; i++) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[2], (4 << 2)|i, m->apicid_bcm5785[1], 0xa + (0+i)%4); //
+	}

// First PCI-E x8
-        for(i = 0; i < 4; i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[5], (0 << 2)|i, m->apicid_bcm5785[1], 0xe); //
-        }
+	for(i = 0; i < 4; i++) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[5], (0 << 2)|i, m->apicid_bcm5785[1], 0xe); //
+	}

// Second PCI-E x8
-        for(i = 0; i < 4; i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[3], (0 << 2)|i, m->apicid_bcm5785[1], 0xc); //
-        }
+	for(i = 0; i < 4; i++) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[3], (0 << 2)|i, m->apicid_bcm5785[1], 0xc); //
+	}

// Third PCI-E x1
-        for(i = 0; i < 4; i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[4], (0 << 2)|i, m->apicid_bcm5785[1], 0xd); //
-        }
+	for(i = 0; i < 4; i++) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[4], (0 << 2)|i, m->apicid_bcm5785[1], 0xd); //
+	}

/*Local Ints:  Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN#*/
-       mptable_lintsrc(mc, bus_isa);
-       /* There is no extension information... */
+	mptable_lintsrc(mc, bus_isa);
+	/* There is no extension information... */

-       /* Compute the checksums */
-       return mptable_finalize(mc);
+	/* Compute the checksums */
+	return mptable_finalize(mc);
 }

unsigned long write_smp_table(unsigned long addr)
 {
-       void *v;
-       v = smp_write_floating_table(addr, 0);
-       return (unsigned long)smp_write_config_table(v);
+	void *v;
+	v = smp_write_floating_table(addr, 0);
+	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/roda/rk886ex/mptable.c b/src/mainboard/roda/rk886ex/mptable.c
index 8e792b7..a9e8a26 100644
--- a/src/mainboard/roda/rk886ex/mptable.c
+++ b/src/mainboard/roda/rk886ex/mptable.c
@@ -24,14 +24,14 @@

static void *smp_write_config_table(void *v)
 {
-        struct mp_config_table *mc;
+	struct mp_config_table *mc;
    int isa_bus;

-        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);

mptable_init(mc, LOCAL_APIC_ADDR);

-        smp_write_processors(mc);
+	smp_write_processors(mc);

mptable_write_buses(mc, NULL, &isa_bus);

diff --git a/src/mainboard/siemens/sitemp_g1p1/mptable.c b/src/mainboard/siemens/sitemp_g1p1/mptable.c
index 1ae48f3..832a79e 100644
--- a/src/mainboard/siemens/sitemp_g1p1/mptable.c
+++ b/src/mainboard/siemens/sitemp_g1p1/mptable.c
@@ -35,7 +35,7 @@ static void *smp_write_config_table(void *v)
    struct mp_config_table *mc;
    int isa_bus;

-        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
    mptable_init(mc, LOCAL_APIC_ADDR);
    smp_write_processors(mc);

diff --git a/src/mainboard/sunw/ultra40/mptable.c b/src/mainboard/sunw/ultra40/mptable.c
index d4fdfc1..5e9c90b 100644
--- a/src/mainboard/sunw/ultra40/mptable.c
+++ b/src/mainboard/sunw/ultra40/mptable.c
@@ -5,56 +5,56 @@
 #include <stdint.h>
 #include <cpu/amd/amdk8_sysconf.h>

-extern  unsigned char bus_ck804_0; //1
-extern  unsigned char bus_ck804_1; //2
-extern  unsigned char bus_ck804_2; //3
-extern  unsigned char bus_ck804_3; //4
-extern  unsigned char bus_ck804_4; //5
-extern  unsigned char bus_ck804_5; //6
-extern  unsigned char bus_8131_0;  //7
-extern  unsigned char bus_8131_1;  //8
-extern  unsigned char bus_8131_2;  //9
-extern  unsigned char bus_ck804b_0;//a
-extern  unsigned char bus_ck804b_1;//b
-extern  unsigned char bus_ck804b_2;//c
-extern  unsigned char bus_ck804b_3;//d
-extern  unsigned char bus_ck804b_4;//e
-extern  unsigned char bus_ck804b_5;//f
-extern  unsigned apicid_ck804;
-extern  unsigned apicid_8131_1;
-extern  unsigned apicid_8131_2;
-extern  unsigned apicid_ck804b;
+extern unsigned char bus_ck804_0; //1
+extern unsigned char bus_ck804_1; //2
+extern unsigned char bus_ck804_2; //3
+extern unsigned char bus_ck804_3; //4
+extern unsigned char bus_ck804_4; //5
+extern unsigned char bus_ck804_5; //6
+extern unsigned char bus_8131_0;  //7
+extern unsigned char bus_8131_1;  //8
+extern unsigned char bus_8131_2;  //9
+extern unsigned char bus_ck804b_0;//a
+extern unsigned char bus_ck804b_1;//b
+extern unsigned char bus_ck804b_2;//c
+extern unsigned char bus_ck804b_3;//d
+extern unsigned char bus_ck804b_4;//e
+extern unsigned char bus_ck804b_5;//f
+extern unsigned apicid_ck804;
+extern unsigned apicid_8131_1;
+extern unsigned apicid_8131_2;
+extern unsigned apicid_ck804b;

extern unsigned pci1234[];

-extern  unsigned sbdn;
-extern  unsigned hcdn[];
-extern  unsigned sbdn3;
-extern  unsigned sbdnb;
+extern unsigned sbdn;
+extern unsigned hcdn[];
+extern unsigned sbdn3;
+extern unsigned sbdnb;

static void *smp_write_config_table(void *v)
 {
-        struct mp_config_table *mc;
+	struct mp_config_table *mc;
    int i, bus_isa;

-        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);

mptable_init(mc, LOCAL_APIC_ADDR);

-        smp_write_processors(mc);
+	smp_write_processors(mc);

get_bus_conf();

mptable_write_buses(mc, NULL, &bus_isa);

/*I/O APICs:	APIC ID	Version	State		Address*/
-        {
-                device_t dev;
+	{
+		device_t dev;
    	struct resource *res;
    	uint32_t dword;

-                dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0));
-                if (dev) {
+		dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0));
+		if (dev) {
    		res = find_resource(dev, PCI_BASE_ADDRESS_1);
    		if (res) {
    			smp_write_ioapic(mc, apicid_ck804, 0x11,
@@ -64,126 +64,126 @@ static void *smp_write_config_table(void *v)
    /* Initialize interrupt mapping*/

dword = 0x0120d218;
-	        	pci_write_config32(dev, 0x7c, dword);
+			pci_write_config32(dev, 0x7c, dword);

-		        dword = 0x12008a00;
-		        pci_write_config32(dev, 0x80, dword);
+			dword = 0x12008a00;
+			pci_write_config32(dev, 0x80, dword);

-	        	dword = 0x00080d7d;
-		        pci_write_config32(dev, 0x84, dword);
+			dword = 0x00080d7d;
+			pci_write_config32(dev, 0x84, dword);

-                }
+		}

-                dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
-                if (dev) {
+		dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
+		if (dev) {
    		res = find_resource(dev, PCI_BASE_ADDRESS_0);
    		if (res) {
    			smp_write_ioapic(mc, apicid_8131_1, 0x11,
    					 res2mmio(res, 0, 0));
    		}
-                }
-                dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
-                if (dev) {
+		}
+		dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
+		if (dev) {
    		res = find_resource(dev, PCI_BASE_ADDRESS_0);
    		if (res) {
    			smp_write_ioapic(mc, apicid_8131_2, 0x11,
    					 res2mmio(res, 0, 0));
    		}
-                }
-
-	    if(pci1234[2] & 0xf) {
-                dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x1,0));
-                if (dev) {
-			res = find_resource(dev, PCI_BASE_ADDRESS_1);
-			if (res) {
-				smp_write_ioapic(mc, apicid_ck804b, 0x11,
+		}
+
+		if(pci1234[2] & 0xf) {
+			dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x1,0));
+			if (dev) {
+				res = find_resource(dev, PCI_BASE_ADDRESS_1);
+				if (res) {
+					smp_write_ioapic(mc, apicid_ck804b, 0x11,
    					 res2mmio(res, 0, 0));
-			}
+				}

-			dword = 0x0000d218;
-                        pci_write_config32(dev, 0x7c, dword);
+				dword = 0x0000d218;
+				pci_write_config32(dev, 0x7c, dword);

-                        dword = 0x00000000;
-                        pci_write_config32(dev, 0x80, dword);
+				dword = 0x00000000;
+				pci_write_config32(dev, 0x80, dword);

-                        dword = 0x00000d00;
-                        pci_write_config32(dev, 0x84, dword);
+				dword = 0x00000d00;
+				pci_write_config32(dev, 0x84, dword);

-                }
-	    }
+			}
+		}

}

mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 1);

// Onboard ck804 smbus
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa);
 // 10

// Onboard ck804 USB 1.1
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21

// Onboard ck804 USB 2
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20

// Onboard ck804 Audio
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+4)<<2)|0, apicid_ck804, 0x14); // 20
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+4)<<2)|0, apicid_ck804, 0x14); // 20

// Onboard ck804 SATA 0
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23

// Onboard ck804 SATA 1
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22

// Onboard ck804 NIC
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +0x0a)<<2)|0, apicid_ck804, 0x15); // 21
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +0x0a)<<2)|0, apicid_ck804, 0x15); // 21

//Slot 1 PCIE x16
-        for(i = 0; i < 4; i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00 << 2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4);
-        }
+	for(i = 0; i < 4; i++) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00 << 2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4);
+	}

//Onboard Firewire
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x05 << 2)|0, apicid_ck804, 0x13); // 19
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x05 << 2)|0, apicid_ck804, 0x13); // 19

//Slot 2 PCI 32
-        for(i = 0; i < 4; i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04 << 2)|i, apicid_ck804, 0x10 + (0+i)%4);
-        }
+	for(i = 0; i < 4; i++) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04 << 2)|i, apicid_ck804, 0x10 + (0+i)%4);
+	}

if(pci1234[2] & 0xf) {
 //Onboard ck804b NIC
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_0, ((sbdnb+0x0a)<<2)|0, apicid_ck804b, 0x15);//24+4+4+21 = 53
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_0, ((sbdnb+0x0a)<<2)|0, apicid_ck804b, 0x15);//24+4+4+21 = 53

//Slot 3 PCIE x16
-        for(i = 0; i < 4; i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00 << 2)|i, apicid_ck804b, 0x10 + (2+i+4-sbdnb%4)%4);
-        }
+	for(i = 0; i < 4; i++) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00 << 2)|i, apicid_ck804b, 0x10 + (2+i+4-sbdnb%4)%4);
+	}
    }

//Channel B of 8131

//Slot 4 PCI-X 100/66
-        for(i = 0; i < 4; i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4 << 2)|i, apicid_8131_2, (0+i)%4);
-        }
+	for(i = 0; i < 4; i++) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4 << 2)|i, apicid_8131_2, (0+i)%4);
+	}

//Slot 5 PCIX 100/66
-        for(i = 0; i < 4; i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9 << 2)|i, apicid_8131_2, (1+i)%4); // 29
-        }
+	for(i = 0; i < 4; i++) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9 << 2)|i, apicid_8131_2, (1+i)%4); // 29
+	}

//OnBoard LSI SCSI
-        for(i = 0; i < 2; i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6 << 2)|i, apicid_8131_2, (2+i)%4); //30
-        }
+	for(i = 0; i < 2; i++) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6 << 2)|i, apicid_8131_2, (2+i)%4); //30
+	}

//Channel A of 8131

//Slot 6 PCIX 133/100/66
-        for(i = 0; i < 4; i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4 << 2)|i, apicid_8131_1, (0+i)%4); //24
-        }
+	for(i = 0; i < 4; i++) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4 << 2)|i, apicid_8131_1, (0+i)%4); //24
+	}

/*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
    mptable_lintsrc(mc, bus_isa);
diff --git a/src/mainboard/supermicro/h8dme/mptable.c b/src/mainboard/supermicro/h8dme/mptable.c
index a76cf1b..9b73c11 100644
--- a/src/mainboard/supermicro/h8dme/mptable.c
+++ b/src/mainboard/supermicro/h8dme/mptable.c
@@ -30,15 +30,15 @@ extern unsigned char bus_pcix[3]; // under bus_mcp55_2

static void *smp_write_config_table(void *v)
 {
-        struct mp_config_table *mc;
+	struct mp_config_table *mc;
    unsigned sbdn;
    int i, j, bus_isa;

-        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);

mptable_init(mc, LOCAL_APIC_ADDR);

-        smp_write_processors(mc);
+	smp_write_processors(mc);

get_bus_conf();
    sbdn = sysconf.sbdn;
@@ -46,13 +46,13 @@ static void *smp_write_config_table(void *v)
    mptable_write_buses(mc, NULL, &bus_isa);

/*I/O APICs:	APIC ID	Version	State		Address*/
-        {
-                device_t dev;
+	{
+		device_t dev;
    	struct resource *res;
    	uint32_t dword;

-                dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
-                if (dev) {
+		dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
+		if (dev) {
    		res = find_resource(dev, PCI_BASE_ADDRESS_1);
    		if (res) {
    			smp_write_ioapic(mc, apicid_mcp55, 0x11,
@@ -60,15 +60,15 @@ static void *smp_write_config_table(void *v)
    		}

dword = 0x43c6c643;
-	        	pci_write_config32(dev, 0x7c, dword);
+			pci_write_config32(dev, 0x7c, dword);

-		        dword = 0x81001a00;
-		        pci_write_config32(dev, 0x80, dword);
+			dword = 0x81001a00;
+			pci_write_config32(dev, 0x80, dword);

-	        	dword = 0xd00012d2;
-		        pci_write_config32(dev, 0x84, dword);
+			dword = 0xd00012d2;
+			pci_write_config32(dev, 0x84, dword);

-                }
+		}

@@ -76,31 +76,31 @@ static void *smp_write_config_table(void *v)

mptable_add_isa_interrupts(mc, bus_isa, apicid_mcp55, 0);

-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+1)<<2)|1, apicid_mcp55, 0xa);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+1)<<2)|1, apicid_mcp55, 0xa);

-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+2)<<2)|0, apicid_mcp55, 0x16); // 22
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+2)<<2)|0, apicid_mcp55, 0x16); // 22

-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+2)<<2)|1, apicid_mcp55, 0x17); // 23
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+2)<<2)|1, apicid_mcp55, 0x17); // 23

-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+6)<<2)|1, apicid_mcp55, 0x17); // 23
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+6)<<2)|1, apicid_mcp55, 0x17); // 23

-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|0, apicid_mcp55, 0x14); // 20
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|1, apicid_mcp55, 0x17); // 23
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|2, apicid_mcp55, 0x15); // 21
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|0, apicid_mcp55, 0x14); // 20
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|1, apicid_mcp55, 0x17); // 23
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|2, apicid_mcp55, 0x15); // 21

-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+8)<<2)|0, apicid_mcp55, 0x16); // 22
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+9)<<2)|0, apicid_mcp55, 0x15); // 21
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+8)<<2)|0, apicid_mcp55, 0x16); // 22
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+9)<<2)|0, apicid_mcp55, 0x15); // 21

for(j = 7; j >= 2; j--) {
    	if(!bus_mcp55[j]) continue;
-	        for(i = 0; i < 4; i++) {
-        	        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[j], (0x00 << 2)|i, apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
-        	}
+		for(i = 0; i < 4; i++) {
+			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[j], (0x00 << 2)|i, apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
+		}
    }

-        for(i = 0; i < 4; i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[1], (0x04 << 2)|i, apicid_mcp55, 0x10 + (0+i)%4);
-        }
+	for(i = 0; i < 4; i++) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[1], (0x04 << 2)|i, apicid_mcp55, 0x10 + (0+i)%4);
+	}

if(bus_pcix[0]) {
diff --git a/src/mainboard/supermicro/h8dmr/mptable.c b/src/mainboard/supermicro/h8dmr/mptable.c
index 7ca1091..61be452 100644
--- a/src/mainboard/supermicro/h8dmr/mptable.c
+++ b/src/mainboard/supermicro/h8dmr/mptable.c
@@ -30,15 +30,15 @@ extern unsigned char bus_pcix[3]; // under bus_mcp55_2

static void *smp_write_config_table(void *v)
 {
-        struct mp_config_table *mc;
+	struct mp_config_table *mc;
    unsigned sbdn;
    int i, j, bus_isa;

-        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);

mptable_init(mc, LOCAL_APIC_ADDR);

-        smp_write_processors(mc);
+	smp_write_processors(mc);

get_bus_conf();
    sbdn = sysconf.sbdn;
@@ -46,13 +46,13 @@ static void *smp_write_config_table(void *v)
    mptable_write_buses(mc, NULL, &bus_isa);

/*I/O APICs:	APIC ID	Version	State		Address*/
-        {
-                device_t dev;
+	{
+		device_t dev;
    	struct resource *res;
    	uint32_t dword;

-                dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
-                if (dev) {
+		dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
+		if (dev) {
    		res = find_resource(dev, PCI_BASE_ADDRESS_1);
    		if (res) {
    			smp_write_ioapic(mc, apicid_mcp55, 0x11,
@@ -60,15 +60,15 @@ static void *smp_write_config_table(void *v)
    		}

dword = 0x43c6c643;
-	        	pci_write_config32(dev, 0x7c, dword);
+			pci_write_config32(dev, 0x7c, dword);

-		        dword = 0x81001a00;
-		        pci_write_config32(dev, 0x80, dword);
+			dword = 0x81001a00;
+			pci_write_config32(dev, 0x80, dword);

-	        	dword = 0xd00012d2;
-		        pci_write_config32(dev, 0x84, dword);
+			dword = 0xd00012d2;
+			pci_write_config32(dev, 0x84, dword);

-                }
+		}

@@ -77,31 +77,31 @@ static void *smp_write_config_table(void *v)
    mptable_add_isa_interrupts(mc, bus_isa, apicid_mcp55, 0);

/*I/O Ints:	Type	Polarity    Trigger			Bus ID	 IRQ	APIC ID	PIN# */
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+1)<<2)|1, apicid_mcp55, 0xa);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+1)<<2)|1, apicid_mcp55, 0xa);

-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+2)<<2)|0, apicid_mcp55, 0x16); // 22
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+2)<<2)|0, apicid_mcp55, 0x16); // 22

-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+2)<<2)|1, apicid_mcp55, 0x17); // 23
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+2)<<2)|1, apicid_mcp55, 0x17); // 23

-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+6)<<2)|1, apicid_mcp55, 0x17); // 23
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+6)<<2)|1, apicid_mcp55, 0x17); // 23

-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|0, apicid_mcp55, 0x14); // 20
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|1, apicid_mcp55, 0x17); // 23
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|2, apicid_mcp55, 0x15); // 21
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|0, apicid_mcp55, 0x14); // 20
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|1, apicid_mcp55, 0x17); // 23
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|2, apicid_mcp55, 0x15); // 21

-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+8)<<2)|0, apicid_mcp55, 0x16); // 22
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+9)<<2)|0, apicid_mcp55, 0x15); // 21
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+8)<<2)|0, apicid_mcp55, 0x16); // 22
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+9)<<2)|0, apicid_mcp55, 0x15); // 21

for(j = 7; j >= 2; j--) {
    	if(!bus_mcp55[j]) continue;
-	        for(i = 0; i < 4; i++) {
-        	        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[j], (0x00 << 2)|i, apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
-        	}
+		for(i = 0; i < 4; i++) {
+			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[j], (0x00 << 2)|i, apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
+		}
    }

-        for(i = 0; i < 4; i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[1], (0x04 << 2)|i, apicid_mcp55, 0x10 + (0+i)%4);
-        }
+	for(i = 0; i < 4; i++) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[1], (0x04 << 2)|i, apicid_mcp55, 0x10 + (0+i)%4);
+	}

if(bus_pcix[0]) {
diff --git a/src/mainboard/supermicro/h8dmr_fam10/mptable.c b/src/mainboard/supermicro/h8dmr_fam10/mptable.c
index 631ff7d..727837f 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/mptable.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/mptable.c
@@ -79,7 +79,7 @@ static void *smp_write_config_table(void *v)

smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0x17); // 23

-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+6)<<2)|1, m->apicid_mcp55, 0x17); // 23
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+6)<<2)|1, m->apicid_mcp55, 0x17); // 23

smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x14); // 20
    smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0x17); // 23