Edward O'Callaghan (eocallaghan@alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7171
-gerrit
commit 51810483821105e8fd0eb848e86bb13f53a4c503 Author: Edward O'Callaghan eocallaghan@alterapraxis.com Date: Thu Oct 23 02:34:06 2014 +1100
southbridge/nvidia: Don't hide pointers behind typedefs
Change-Id: I1ea9d47749365936da6198861daa6e5c7ef6bfa7 Signed-off-by: Edward O'Callaghan eocallaghan@alterapraxis.com --- src/southbridge/nvidia/ck804/ck804.c | 10 +++++----- src/southbridge/nvidia/ck804/lpc.c | 18 +++++++++--------- src/southbridge/nvidia/ck804/smbus.c | 8 ++++---- src/southbridge/nvidia/mcp55/azalia.c | 2 +- src/southbridge/nvidia/mcp55/lpc.c | 14 +++++++------- src/southbridge/nvidia/mcp55/mcp55.c | 10 +++++----- src/southbridge/nvidia/mcp55/mcp55.h | 2 +- src/southbridge/nvidia/mcp55/smbus.c | 12 ++++++------ 8 files changed, 38 insertions(+), 38 deletions(-)
diff --git a/src/southbridge/nvidia/ck804/ck804.c b/src/southbridge/nvidia/ck804/ck804.c index 353a4bd..a285938 100644 --- a/src/southbridge/nvidia/ck804/ck804.c +++ b/src/southbridge/nvidia/ck804/ck804.c @@ -28,9 +28,9 @@
static u32 final_reg;
-static device_t find_lpc_dev(device_t dev, unsigned devfn) +static struct device * find_lpc_dev(struct device * dev, unsigned devfn) { - device_t lpc_dev; + struct device * lpc_dev;
lpc_dev = dev_find_slot(dev->bus->secondary, devfn); if (!lpc_dev) @@ -57,9 +57,9 @@ static device_t find_lpc_dev(device_t dev, unsigned devfn) return lpc_dev; }
-void ck804_enable(device_t dev) +void ck804_enable(struct device * dev) { - device_t lpc_dev; + struct device * lpc_dev; unsigned index = 0, index2 = 0, deviceid, vendorid, devfn; u32 reg_old, reg; u8 byte; @@ -188,7 +188,7 @@ void ck804_enable(device_t dev) } }
-static void ck804_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void ck804_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index b68785a..c425a26 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -52,7 +52,7 @@ #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif
-static void lpc_common_init(device_t dev) +static void lpc_common_init(struct device * dev) { u32 dword; struct resource *res; @@ -69,12 +69,12 @@ static void lpc_common_init(device_t dev) #endif }
-static void lpc_slave_init(device_t dev) +static void lpc_slave_init(struct device * dev) { lpc_common_init(dev); }
-static void rom_dummy_write(device_t dev) +static void rom_dummy_write(struct device * dev) { u8 old, new; u8 *p; @@ -104,7 +104,7 @@ static void rom_dummy_write(device_t dev)
unsigned pm_base = 0;
-static void lpc_init(device_t dev) +static void lpc_init(struct device * dev) { u8 byte, byte_old; int on, nmi_option; @@ -170,7 +170,7 @@ static void lpc_init(device_t dev) rom_dummy_write(dev); }
-static void ck804_lpc_read_resources(device_t dev) +static void ck804_lpc_read_resources(struct device * dev) { struct resource *res; unsigned long index; @@ -215,7 +215,7 @@ static void ck804_lpc_read_resources(device_t dev) } }
-static void ck804_lpc_set_resources(device_t dev) +static void ck804_lpc_set_resources(struct device * dev) { u8 byte; struct resource *res; @@ -251,7 +251,7 @@ static void ck804_lpc_set_resources(device_t dev) * This function is called by the global enable_resources() indirectly via the * device_operation::enable_resources() method of devices. */ -static void ck804_lpc_enable_childrens_resources(device_t dev) +static void ck804_lpc_enable_childrens_resources(struct device * dev) { struct bus *link; u32 reg, reg_var[4]; @@ -260,7 +260,7 @@ static void ck804_lpc_enable_childrens_resources(device_t dev) reg = pci_read_config32(dev, 0xa0);
for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device * child; for (child = link->children; child; child = child->sibling) { if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; @@ -307,7 +307,7 @@ static void ck804_lpc_enable_childrens_resources(device_t dev) pci_write_config32(dev, 0xa8 + i * 4, reg_var[i]); }
-static void ck804_lpc_enable_resources(device_t dev) +static void ck804_lpc_enable_resources(struct device * dev) { pci_dev_enable_resources(dev); ck804_lpc_enable_childrens_resources(dev); diff --git a/src/southbridge/nvidia/ck804/smbus.c b/src/southbridge/nvidia/ck804/smbus.c index dd6a5f4..62967bf 100644 --- a/src/southbridge/nvidia/ck804/smbus.c +++ b/src/southbridge/nvidia/ck804/smbus.c @@ -28,7 +28,7 @@ #include "ck804.h" #include "smbus.h"
-static int lsmbus_recv_byte(device_t dev) +static int lsmbus_recv_byte(struct device * dev) { unsigned device; struct resource *res; @@ -42,7 +42,7 @@ static int lsmbus_recv_byte(device_t dev) return do_smbus_recv_byte(res->base, device); }
-static int lsmbus_send_byte(device_t dev, u8 val) +static int lsmbus_send_byte(struct device * dev, u8 val) { unsigned device; struct resource *res; @@ -56,7 +56,7 @@ static int lsmbus_send_byte(device_t dev, u8 val) return do_smbus_send_byte(res->base, device, val); }
-static int lsmbus_read_byte(device_t dev, u8 address) +static int lsmbus_read_byte(struct device * dev, u8 address) { unsigned device; struct resource *res; @@ -70,7 +70,7 @@ static int lsmbus_read_byte(device_t dev, u8 address) return do_smbus_read_byte(res->base, device, address); }
-static int lsmbus_write_byte(device_t dev, u8 address, u8 val) +static int lsmbus_write_byte(struct device * dev, u8 address, u8 val) { unsigned device; struct resource *res; diff --git a/src/southbridge/nvidia/mcp55/azalia.c b/src/southbridge/nvidia/mcp55/azalia.c index 67433d3..954e305 100644 --- a/src/southbridge/nvidia/mcp55/azalia.c +++ b/src/southbridge/nvidia/mcp55/azalia.c @@ -254,7 +254,7 @@ static void azalia_init(struct device *dev) } }
-static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void azalia_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index ef3c6f6..4537ad5 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -57,7 +57,7 @@ #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif
-static void lpc_common_init(device_t dev, int master) +static void lpc_common_init(struct device * dev, int master) { u8 byte; u32 ioapic_base; @@ -74,7 +74,7 @@ static void lpc_common_init(device_t dev, int master) clear_ioapic(ioapic_base); }
-static void lpc_slave_init(device_t dev) +static void lpc_slave_init(struct device * dev) { lpc_common_init(dev, 0); } @@ -88,7 +88,7 @@ static void enable_hpet(struct device *dev) printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address); }
-static void lpc_init(device_t dev) +static void lpc_init(struct device * dev) { u8 byte, byte_old; int on, nmi_option; @@ -161,7 +161,7 @@ static void lpc_init(device_t dev) enable_hpet(dev); }
-static void mcp55_lpc_read_resources(device_t dev) +static void mcp55_lpc_read_resources(struct device * dev) { struct resource *res;
@@ -193,7 +193,7 @@ static void mcp55_lpc_read_resources(device_t dev) * * @param dev The device whose children's resources are to be enabled. */ -static void mcp55_lpc_enable_childrens_resources(device_t dev) +static void mcp55_lpc_enable_childrens_resources(struct device * dev) { u32 reg, reg_var[4]; int i, var_num = 0; @@ -202,7 +202,7 @@ static void mcp55_lpc_enable_childrens_resources(device_t dev) reg = pci_read_config32(dev, 0xa0);
for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device * child; for (child = link->children; child; child = child->sibling) { if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; @@ -250,7 +250,7 @@ static void mcp55_lpc_enable_childrens_resources(device_t dev) pci_write_config32(dev, 0xa8 + i * 4, reg_var[i]); }
-static void mcp55_lpc_enable_resources(device_t dev) +static void mcp55_lpc_enable_resources(struct device * dev) { pci_dev_enable_resources(dev); mcp55_lpc_enable_childrens_resources(dev); diff --git a/src/southbridge/nvidia/mcp55/mcp55.c b/src/southbridge/nvidia/mcp55/mcp55.c index 8350579..d577383 100644 --- a/src/southbridge/nvidia/mcp55/mcp55.c +++ b/src/southbridge/nvidia/mcp55/mcp55.c @@ -31,9 +31,9 @@
static u32 final_reg;
-static device_t find_lpc_dev(device_t dev, unsigned devfn) +static struct device * find_lpc_dev(struct device * dev, unsigned devfn) { - device_t lpc_dev; + struct device * lpc_dev;
lpc_dev = dev_find_slot(dev->bus->secondary, devfn);
@@ -58,9 +58,9 @@ static device_t find_lpc_dev(device_t dev, unsigned devfn) return lpc_dev; }
-void mcp55_enable(device_t dev) +void mcp55_enable(struct device * dev) { - device_t lpc_dev = 0, sm_dev = 0; + struct device * lpc_dev = 0, sm_dev = 0; unsigned index = 0, index2 = 0; u32 reg_old, reg; u8 byte; @@ -234,7 +234,7 @@ void mcp55_enable(device_t dev) } }
-static void mcp55_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void mcp55_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/nvidia/mcp55/mcp55.h b/src/southbridge/nvidia/mcp55/mcp55.h index 4fb3391..20b33b4 100644 --- a/src/southbridge/nvidia/mcp55/mcp55.h +++ b/src/southbridge/nvidia/mcp55/mcp55.h @@ -30,7 +30,7 @@
#ifndef __PRE_RAM__ #include "chip.h" -void mcp55_enable(device_t dev); +void mcp55_enable(struct device * dev); extern struct pci_operations mcp55_pci_ops; #else void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); diff --git a/src/southbridge/nvidia/mcp55/smbus.c b/src/southbridge/nvidia/mcp55/smbus.c index 3e0b87e..e28a896 100644 --- a/src/southbridge/nvidia/mcp55/smbus.c +++ b/src/southbridge/nvidia/mcp55/smbus.c @@ -31,7 +31,7 @@ #include "mcp55.h" #include "smbus.h"
-static int lsmbus_recv_byte(device_t dev) +static int lsmbus_recv_byte(struct device * dev) { unsigned device; struct resource *res; @@ -45,7 +45,7 @@ static int lsmbus_recv_byte(device_t dev) return do_smbus_recv_byte(res->base, device); }
-static int lsmbus_send_byte(device_t dev, u8 val) +static int lsmbus_send_byte(struct device * dev, u8 val) { unsigned device; struct resource *res; @@ -59,7 +59,7 @@ static int lsmbus_send_byte(device_t dev, u8 val) return do_smbus_send_byte(res->base, device, val); }
-static int lsmbus_read_byte(device_t dev, u8 address) +static int lsmbus_read_byte(struct device * dev, u8 address) { unsigned device; struct resource *res; @@ -73,7 +73,7 @@ static int lsmbus_read_byte(device_t dev, u8 address) return do_smbus_read_byte(res->base, device, address); }
-static int lsmbus_write_byte(device_t dev, u8 address, u8 val) +static int lsmbus_write_byte(struct device * dev, u8 address, u8 val) { unsigned device; struct resource *res; @@ -97,7 +97,7 @@ static struct smbus_bus_operations lops_smbus_bus = { unsigned pm_base; #endif
-static void mcp55_sm_read_resources(device_t dev) +static void mcp55_sm_read_resources(struct device * dev) { unsigned long index;
@@ -110,7 +110,7 @@ static void mcp55_sm_read_resources(device_t dev) compact_resources(dev); }
-static void mcp55_sm_init(device_t dev) +static void mcp55_sm_init(struct device * dev) { #if CONFIG_HAVE_ACPI_TABLES struct resource *res;