[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode

[Aamir Bohra (Code Review)]

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43494 )

Change subject: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode
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Patch Set 7:

(3 comments)

https://review.coreboot.org/c/coreboot/+/43494/1/src/soc/intel/common/block/... 
File src/soc/intel/common/block/cpu/car/cache_as_ram.S:

https://review.coreboot.org/c/coreboot/+/43494/1/src/soc/intel/common/block/... 
PS1, Line 371: 	 * Data Size (RW) : Up to 256K
> Yes..however way size depends on the total LLC and number of ways that a platform supports. […]

Done

https://review.coreboot.org/c/coreboot/+/43494/1/src/soc/intel/common/block/... 
PS1, Line 429: 	movl	$0x02, %edx
> COS is mapped to 32:33 of the MSR 0xCF8 , that is why assigning it to EDX.

Done

https://review.coreboot.org/c/coreboot/+/43494/1/src/soc/intel/common/block/... 
PS1, Line 445: 	movl	$0x01, %edx
> same above

Done