[coreboot-gerrit] Change in coreboot[master]: soc/intel/xeon_sp: Lock down DMI3 PCI registers

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47448 )

Change subject: soc/intel/xeon_sp: Lock down DMI3 PCI registers
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Patch Set 6:

(1 comment)

https://review.coreboot.org/c/coreboot/+/47448/6/src/soc/intel/xeon_sp/skx/i... 
File src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h:

https://review.coreboot.org/c/coreboot/+/47448/6/src/soc/intel/xeon_sp/skx/i... 
PS6, Line 181: #define ERRINJCON		0x1d8
CPX has an extra \n here