[coreboot-gerrit] Change in coreboot[master]: amd/padmelon: Enable DRAM

[John E. Kabat (Code Review)]

Hello Marshall Dawson,

I'd like you to do a code review. Please visit

https://review.coreboot.org/21036

to review the following change.

Change subject: amd/padmelon: Enable DRAM
......................................................................

amd/padmelon: Enable DRAM

Use the normal SPD read callout function.  Remove the
board-specific function for SPD.

Remove the board_id check for the AmdInitPost DDR configuration.

Change to a single DIMM per channel and update the devicetree
accordingly.

Change-Id: I3f0cf3c24a9d0311432f9224b45296ef5167ed91
Signed-off-by: Marshall Dawson 
---
M src/mainboard/amd/padmelon/BiosCallOuts.c
M src/mainboard/amd/padmelon/OemCustomize.c
M src/mainboard/amd/padmelon/devicetree.cb
3 files changed, 6 insertions(+), 47 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/21036/1

diff --git a/src/mainboard/amd/padmelon/BiosCallOuts.c b/src/mainboard/amd/padmelon/BiosCallOuts.c
index 08e5ea6..ac18f94 100644
--- a/src/mainboard/amd/padmelon/BiosCallOuts.c
+++ b/src/mainboard/amd/padmelon/BiosCallOuts.c
@@ -34,14 +34,13 @@
 #include <boardid.h>

static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr);
-static AGESA_STATUS board_ReadSpd(UINT32 Func, UINTN Data, VOID *ConfigPtr);

const BIOS_CALLOUT_STRUCT BiosCallouts[] =
 {
    {AGESA_ALLOCATE_BUFFER,          agesa_AllocateBuffer },
    {AGESA_DEALLOCATE_BUFFER,        agesa_DeallocateBuffer },
    {AGESA_LOCATE_BUFFER,            agesa_LocateBuffer },
-	{AGESA_READ_SPD,                 board_ReadSpd },
+	{AGESA_READ_SPD,                 agesa_ReadSpd },
    {AGESA_DO_RESET,                 agesa_Reset },
    {AGESA_READ_SPD_RECOVERY,        agesa_NoopUnsupported },
    {AGESA_RUNFUNC_ONAP,             agesa_RunFuncOnAp },
@@ -100,42 +99,5 @@
    }
    printk(BIOS_DEBUG, "Done\n");

-	return AGESA_SUCCESS;
-}
-
-static AGESA_STATUS board_ReadSpd(UINT32 Func, UINTN Data, VOID *ConfigPtr)
-{
-#ifdef __PRE_RAM__
-	int spdAddress;
-	AGESA_READ_SPD_PARAMS *info = ConfigPtr;
-
-	DEVTREE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
-	DEVTREE_CONST struct northbridge_amd_pi_00660F01_config *config = dev->chip_info;
-	UINT8 spdAddrLookup_rev_F [2][2][4]= {
-		{ {0xA0, 0xA2}, {0xA4, 0xAC}, }, /* socket 0 - Channel 0 & 1 - 8-bit SPD addresses */
-		{ {0x00, 0x00}, {0x00, 0x00}, }, /* socket 1 - Channel 0 & 1 - 8-bit SPD addresses */
-	};
-
-	if ((dev == 0) || (config == 0))
-		return AGESA_ERROR;
-	if (info->SocketId >= ARRAY_SIZE(config->spdAddrLookup))
-		return AGESA_ERROR;
-	if (info->MemChannelId >= ARRAY_SIZE(config->spdAddrLookup[0]))
-		return AGESA_ERROR;
-	if (info->DimmId >= ARRAY_SIZE(config->spdAddrLookup[0][0]))
-		return AGESA_ERROR;
-	if (board_id() == 'F')
-		spdAddress = spdAddrLookup_rev_F
-			[info->SocketId] [info->MemChannelId] [info->DimmId];
-	else
-		spdAddress = config->spdAddrLookup
-			[info->SocketId] [info->MemChannelId] [info->DimmId];
-
-	if (spdAddress == 0)
-		return AGESA_ERROR;
-	int err = hudson_readSpd(spdAddress, (void *) info->Buffer, 128);
-	if (err)
-		return AGESA_ERROR;
-#endif
    return AGESA_SUCCESS;
 }
diff --git a/src/mainboard/amd/padmelon/OemCustomize.c b/src/mainboard/amd/padmelon/OemCustomize.c
index 8d1ad4b..3d1d20c 100644
--- a/src/mainboard/amd/padmelon/OemCustomize.c
+++ b/src/mainboard/amd/padmelon/OemCustomize.c
@@ -137,7 +137,7 @@

static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = {
    DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY),
-	NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
+	NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
    NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
    MOTHER_BOARD_LAYERS (LAYERS_6),
    MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
@@ -149,7 +149,5 @@

void OemPostParams(AMD_POST_PARAMS *PostParams)
 {
-	if (board_id() == 'F') {
-		PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)DDR4PlatformMemoryConfiguration;
-	}
+	PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)DDR4PlatformMemoryConfiguration;
 }
diff --git a/src/mainboard/amd/padmelon/devicetree.cb b/src/mainboard/amd/padmelon/devicetree.cb
index a259e92..5c107e2 100644
--- a/src/mainboard/amd/padmelon/devicetree.cb
+++ b/src/mainboard/amd/padmelon/devicetree.cb
@@ -47,8 +47,8 @@
    				chip drivers/generic/generic #dimm 0-0-0
    					device i2c 50 on end
    				end
-					chip drivers/generic/generic #dimm 0-0-1
-						device i2c 51 on end
+					chip drivers/generic/generic #dimm 0-1-0
+						device i2c 52 on end
    				end
    			end # SM
    			#device pci 14.2 on  end # HDA	0x4383
@@ -64,8 +64,7 @@
    		device pci 18.5 on  end
    		register "spdAddrLookup" = "
    		{
-				{ {0xA0, 0xA4}, {0xA2, 0xA6}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
-				{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
+				{ {0xA0}, {0xA4}, }, // 1 APU socket, 2 channels, 1 DIMM per ch
    		}"

end #chip northbridge/amd/pi/00660F01 # CPU side of HT root complex