[coreboot-gerrit] [XS] Change in coreboot[main]: soc/amd/common/uart: Configure UART PAD

[Naresh Solanki (Code Review)]

Naresh Solanki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86643?usp=email )

Change subject: soc/amd/common/uart: Configure UART PAD
......................................................................

soc/amd/common/uart: Configure UART PAD

On Glinda SoC, UART0 pins like CTS & RTS are also shared with
UART1. During FSP Silicon init, UART1 pins gets reconfigured to UART0
CTS & RTS when initializing it. This leads IOMUX configuration mismatch
for UART1 leading to UART1 non-functional.

To address this, configure UART controller pad when enabling it post
silicon init.

Change-Id: Ie4168e9ea5ecf06e49eace72545d533bf9ab7dcc
Signed-off-by: Naresh Solanki 
---
M src/soc/amd/common/block/uart/uart.c
1 file changed, 5 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/86643/1

diff --git a/src/soc/amd/common/block/uart/uart.c b/src/soc/amd/common/block/uart/uart.c
index ca678fd..4e70b23 100644
--- a/src/soc/amd/common/block/uart/uart.c
+++ b/src/soc/amd/common/block/uart/uart.c
@@ -80,6 +80,9 @@
 static void uart_enable(struct device *dev)
 {
    unsigned int dev_id;
+	unsigned int idx;
+	size_t num_ctrlrs;
+	const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs);

if (get_uart_aoac_device(dev->path.mmio.addr, &dev_id) == CB_ERR) {
    	printk(BIOS_ERR, "%s: Unknown device: %s\n", __func__, dev_path(dev));
@@ -89,6 +92,8 @@
    if (dev->enabled) {
    	power_on_aoac_device(dev_id);
    	wait_for_aoac_enabled(dev_id);
+		if (get_uart_idx(dev->path.mmio.addr, ctrlr, num_ctrlrs, &idx) == CB_SUCCESS)
+			set_uart_config(idx);
    } else {
    	power_off_aoac_device(dev_id);
    }