EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 18:
(3 comments)
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ro... PS17, Line 30: static int pcie_is_flag_enabled(const struct pcie_rp_config pcie_rp, : enum pcie_rp_flags flag_mask) : { : return pcie_rp.flags & flag_mask ? 1 : 0; : }
This can be added as inline to chip.h so that it can be used by both romstage and ramstage files.
Done
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ro... PS17, Line 48: PCH_PCIE_RP
Instead of checking PCH_PCIE_RP, should we add a flag, PCIE_RP_NO_CLKREQ and check that? That will h […]
If CPU root ports never wanted CLKREQ, we don't have to add flags for ever CPU root port. Will CPU root port need CLKREQ?
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ro... PS17, Line 160: disable_unused_clk(m_cfg, config);
You can do this before the pcie_rp_init() calls and then you don't need the special PcieClkSrcDisabl […]
Done