Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36449 )
Change subject: mainboard/google: Allow Hatch variants to read SPD data over SMBus ......................................................................
mainboard/google: Allow Hatch variants to read SPD data over SMBus
All Hatch variants so far embed static SPD data encoded within the firmware image. However we wish the flexibility for romstage implementations that allow for reading the SPD data dynamically over SMBus. This romstage variant allows for reading the SPD data over SMBus.
BRANCH=none BUG=b:143134702 TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: I3516a46b91840a9f6d1f4cffb2553d939d79cda2 Signed-off-by: Edward O'Callaghan quasisec@chromium.org --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Makefile.inc A src/mainboard/google/hatch/romstage_spd_smbus.c 3 files changed, 63 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/36449/1
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 219be22..e339693 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -60,7 +60,11 @@
config ROMSTAGE_SPD_CBFS bool - default y + default y if !ROMSTAGE_SPD_SMBUS + +config ROMSTAGE_SPD_SMBUS + bool + default n
config DRIVER_TPM_SPI_BUS default 0x1 diff --git a/src/mainboard/google/hatch/Makefile.inc b/src/mainboard/google/hatch/Makefile.inc index 3ed82e7..0740c08 100644 --- a/src/mainboard/google/hatch/Makefile.inc +++ b/src/mainboard/google/hatch/Makefile.inc @@ -21,6 +21,7 @@ ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
romstage-$(CONFIG_ROMSTAGE_SPD_CBFS) += romstage_spd_cbfs.c +romstage-$(CONFIG_ROMSTAGE_SPD_SMBUS) += romstage_spd_smbus.c romstage-$(CONFIG_CHROMEOS) += chromeos.c
verstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/mainboard/google/hatch/romstage_spd_smbus.c b/src/mainboard/google/hatch/romstage_spd_smbus.c new file mode 100644 index 0000000..245b61d --- /dev/null +++ b/src/mainboard/google/hatch/romstage_spd_smbus.c @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <soc/cnl_memcfg_init.h> +#include <soc/romstage.h> +#include <variant/gpio.h> +#include <spd_bin.h> +#include <gpio.h> + +/* + * GPIO_MEM_CH_SEL is set to 1 for single channel skus + * and 0 for dual channel skus. + */ +#define GPIO_MEM_CH_SEL GPP_F2 + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + int is_single_ch_mem; + struct cnl_mb_cfg memcfg; + variant_memory_params(&memcfg); + + /* + * GPP_F2 is the MEM_CH_SEL gpio, which is set to 1 for single + * channel skus and 0 for dual channel skus. + */ + is_single_ch_mem = gpio_get(GPIO_MEM_CH_SEL); + + /* Read spd block to get memory config */ + struct spd_block blk = { + .addr_map = { 0x50, 0x52 }, + }; + + memcfg.dq_pins_interleaved = 1; + get_spd_smbus(&blk); + memcfg.spd[0].read_type = READ_SMBUS; + memcfg.spd[0].spd_spec.spd_smbus_address = (uintptr_t)blk.spd_array[0]; + if (!is_single_ch_mem) { + memcfg.spd[1].read_type = READ_SMBUS; + memcfg.spd[1].spd_spec.spd_smbus_address = (uintptr_t)blk.spd_array[1]; + } + dump_spd_info(&blk); + + cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); +}