Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52515 )
Change subject: soc/intel/broadwell: Use Lynx Point IOBP code ......................................................................
soc/intel/broadwell: Use Lynx Point IOBP code
Change-Id: I89832dd6089e1961b4ffdb5661dc98b26a5cb0a2 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/52515 Reviewed-by: Nico Huber nico.h@gmx.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- D src/soc/intel/broadwell/include/soc/iobp.h M src/soc/intel/broadwell/pch/Makefile.inc M src/soc/intel/broadwell/pch/adsp.c D src/soc/intel/broadwell/pch/iobp.c M src/soc/intel/broadwell/pch/lpc.c M src/soc/intel/broadwell/pch/pch.c M src/soc/intel/broadwell/pch/pcie.c M src/soc/intel/broadwell/pch/sata.c M src/soc/intel/broadwell/pch/serialio.c 9 files changed, 8 insertions(+), 158 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/soc/intel/broadwell/include/soc/iobp.h b/src/soc/intel/broadwell/include/soc/iobp.h deleted file mode 100644 index e3a6993..0000000 --- a/src/soc/intel/broadwell/include/soc/iobp.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _BROADWELL_IOBP_H_ -#define _BROADWELL_IOBP_H_ - -u32 pch_iobp_read(u32 address); -void pch_iobp_write(u32 address, u32 data); -void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); -void pch_iobp_exec(u32 addr, u16 op_dcode, u8 route_id, u32 *data, u8 *resp); - -#endif diff --git a/src/soc/intel/broadwell/pch/Makefile.inc b/src/soc/intel/broadwell/pch/Makefile.inc index b345e8d..414c85c 100644 --- a/src/soc/intel/broadwell/pch/Makefile.inc +++ b/src/soc/intel/broadwell/pch/Makefile.inc @@ -9,8 +9,8 @@ smm-y += ../../../../southbridge/intel/lynxpoint/lp_gpio.c ramstage-y += hda.c ramstage-y += ../../../../southbridge/intel/lynxpoint/hda_verb.c -ramstage-y += iobp.c -romstage-y += iobp.c +ramstage-y += ../../../../southbridge/intel/lynxpoint/iobp.c +romstage-y += ../../../../southbridge/intel/lynxpoint/iobp.c ramstage-y += fadt.c ramstage-y += lpc.c ramstage-y += me.c diff --git a/src/soc/intel/broadwell/pch/adsp.c b/src/soc/intel/broadwell/pch/adsp.c index a65ff4b..040bba1 100644 --- a/src/soc/intel/broadwell/pch/adsp.c +++ b/src/soc/intel/broadwell/pch/adsp.c @@ -9,12 +9,12 @@ #include <device/mmio.h> #include <soc/adsp.h> #include <soc/device_nvs.h> -#include <soc/iobp.h> #include <soc/device_nvs.h> #include <soc/pch.h> #include <soc/ramstage.h> #include <soc/rcba.h> #include <soc/intel/broadwell/pch/chip.h> +#include <southbridge/intel/lynxpoint/iobp.h>
static void adsp_init(struct device *dev) { diff --git a/src/soc/intel/broadwell/pch/iobp.c b/src/soc/intel/broadwell/pch/iobp.c deleted file mode 100644 index deb4156..0000000 --- a/src/soc/intel/broadwell/pch/iobp.c +++ /dev/null @@ -1,139 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/console.h> -#include <delay.h> -#include <soc/iobp.h> -#include <soc/rcba.h> - -#define IOBP_RETRY 1000 - -static inline int iobp_poll(void) -{ - unsigned int try; - - for (try = IOBP_RETRY; try > 0; try--) { - u16 status = RCBA16(IOBPS); - if ((status & IOBPS_READY) == 0) - return 1; - udelay(10); - } - - printk(BIOS_ERR, "IOBP: timeout waiting for transaction to complete\n"); - return 0; -} - -u32 pch_iobp_read(u32 address) -{ - u16 status; - - if (!iobp_poll()) - return 0; - - /* Set the address */ - RCBA32(IOBPIRI) = address; - - /* READ OPCODE */ - status = RCBA16(IOBPS); - status &= ~IOBPS_MASK; - status |= IOBPS_READ; - RCBA16(IOBPS) = status; - - /* Undocumented magic */ - RCBA16(IOBPU) = IOBPU_MAGIC; - - /* Set ready bit */ - status = RCBA16(IOBPS); - status |= IOBPS_READY; - RCBA16(IOBPS) = status; - - if (!iobp_poll()) - return 0; - - /* Check for successful transaction */ - status = RCBA16(IOBPS); - if (status & IOBPS_TX_MASK) { - printk(BIOS_ERR, "IOBP: read 0x%08x failed\n", address); - return 0; - } - - /* Read IOBP data */ - return RCBA32(IOBPD); -} - -void pch_iobp_write(u32 address, u32 data) -{ - u16 status; - - if (!iobp_poll()) - return; - - /* Set the address */ - RCBA32(IOBPIRI) = address; - - /* WRITE OPCODE */ - status = RCBA16(IOBPS); - status &= ~IOBPS_MASK; - status |= IOBPS_WRITE; - RCBA16(IOBPS) = status; - - RCBA32(IOBPD) = data; - - /* Undocumented magic */ - RCBA16(IOBPU) = IOBPU_MAGIC; - - /* Set ready bit */ - status = RCBA16(IOBPS); - status |= IOBPS_READY; - RCBA16(IOBPS) = status; - - if (!iobp_poll()) - return; - - /* Check for successful transaction */ - status = RCBA16(IOBPS); - if (status & IOBPS_TX_MASK) { - printk(BIOS_ERR, "IOBP: write 0x%08x failed\n", address); - return; - } - - printk(BIOS_SPEW, "IOBP: set 0x%08x to 0x%08x\n", address, data); -} - -void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) -{ - u32 data = pch_iobp_read(address); - - /* Update the data */ - data &= andvalue; - data |= orvalue; - - pch_iobp_write(address, data); -} - -void pch_iobp_exec(u32 addr, u16 op_code, u8 route_id, u32 *data, u8 *resp) -{ - if (!data || !resp) - return; - - *resp = -1; - if (!iobp_poll()) - return; - - /* RCBA2330[31:0] = Address */ - RCBA32(IOBPIRI) = addr; - /* RCBA2338[15:8] = opcode */ - RCBA16(IOBPS) = (RCBA16(IOBPS) & 0x00ff) | op_code; - /* RCBA233A[15:8] = 0xf0 RCBA233A[7:0] = Route ID */ - RCBA16(IOBPU) = IOBPU_MAGIC | route_id; - - if (op_code == IOBP_PCICFG_WRITE) - RCBA32(IOBPD) = *data; - /* Set RCBA2338[0] to trigger IOBP transaction*/ - RCBA16(IOBPS) = RCBA16(IOBPS) | 0x1; - - if (!iobp_poll()) - return; - - *resp = (RCBA16(IOBPS) & IOBPS_TX_MASK) >> 1; - *data = RCBA32(IOBPD); -} diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c index f7835db..e32ae36 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -11,7 +11,6 @@ #include <arch/ioapic.h> #include <acpi/acpi.h> #include <cpu/x86/smm.h> -#include <soc/iobp.h> #include <soc/iomap.h> #include <soc/lpc.h> #include <soc/pch.h> @@ -22,6 +21,7 @@ #include <soc/intel/broadwell/pch/chip.h> #include <acpi/acpigen.h> #include <southbridge/intel/common/rtc.h> +#include <southbridge/intel/lynxpoint/iobp.h> #include <southbridge/intel/lynxpoint/lp_gpio.h>
static void pch_enable_ioapic(struct device *dev) diff --git a/src/soc/intel/broadwell/pch/pch.c b/src/soc/intel/broadwell/pch/pch.c index d4b88f1..20e2431 100644 --- a/src/soc/intel/broadwell/pch/pch.c +++ b/src/soc/intel/broadwell/pch/pch.c @@ -5,13 +5,13 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_def.h> -#include <soc/iobp.h> #include <soc/pch.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <soc/rcba.h> #include <soc/serialio.h> #include <soc/spi.h> +#include <southbridge/intel/lynxpoint/iobp.h>
u8 pch_revision(void) { diff --git a/src/soc/intel/broadwell/pch/pcie.c b/src/soc/intel/broadwell/pch/pcie.c index 26fde0b..28d858f 100644 --- a/src/soc/intel/broadwell/pch/pcie.c +++ b/src/soc/intel/broadwell/pch/pcie.c @@ -9,11 +9,11 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <soc/lpc.h> -#include <soc/iobp.h> #include <soc/pch.h> #include <soc/pci_devs.h> #include <soc/rcba.h> #include <soc/intel/broadwell/pch/chip.h> +#include <southbridge/intel/lynxpoint/iobp.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> #include <delay.h>
diff --git a/src/soc/intel/broadwell/pch/sata.c b/src/soc/intel/broadwell/pch/sata.c index 82760ab..b8ef527 100644 --- a/src/soc/intel/broadwell/pch/sata.c +++ b/src/soc/intel/broadwell/pch/sata.c @@ -7,11 +7,11 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <delay.h> -#include <soc/iobp.h> #include <soc/ramstage.h> #include <soc/rcba.h> #include <soc/sata.h> #include <soc/intel/broadwell/pch/chip.h> +#include <southbridge/intel/lynxpoint/iobp.h>
static inline u32 sir_read(struct device *dev, int idx) { diff --git a/src/soc/intel/broadwell/pch/serialio.c b/src/soc/intel/broadwell/pch/serialio.c index 28f34b7..fa61b91 100644 --- a/src/soc/intel/broadwell/pch/serialio.c +++ b/src/soc/intel/broadwell/pch/serialio.c @@ -7,7 +7,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <soc/iobp.h> #include <soc/device_nvs.h> #include <soc/pci_devs.h> #include <soc/pch.h> @@ -15,6 +14,7 @@ #include <soc/rcba.h> #include <soc/serialio.h> #include <soc/intel/broadwell/pch/chip.h> +#include <southbridge/intel/lynxpoint/iobp.h>
/* Set D3Hot Power State in ACPI mode */ static void serialio_enable_d3hot(struct resource *res)