Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/29429 )
Change subject: mb/google/poppy/variant/nocturne: use PLTRST for GPP_C11 ......................................................................
mb/google/poppy/variant/nocturne: use PLTRST for GPP_C11
GPP_C11 (FPMCU_INT_L) was set to DEEP, causing problems with S3. Changed GPP_C11 configuration to use PLTRST instead.
BUG=b:114196791 TEST=Build, flash, boot nocturne, log in to kernel and execute the following two commands and verify it passes : echo 0 > /var/lib/power_manager/suspend_to_idle && restart powerd sudo suspend_stress_test -c 2
Change-Id: I008532fce963c51a435378001440ac72b5ebfffc Signed-off-by: Nick Vaccaro nvaccaro@google.com Reviewed-on: https://review.coreboot.org/29429 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/mainboard/google/poppy/variants/nocturne/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/mainboard/google/poppy/variants/nocturne/gpio.c b/src/mainboard/google/poppy/variants/nocturne/gpio.c index 16ff982..9aa7706 100644 --- a/src/mainboard/google/poppy/variants/nocturne/gpio.c +++ b/src/mainboard/google/poppy/variants/nocturne/gpio.c @@ -135,7 +135,7 @@ /* C10 : UART0_RTS# ==> PCH_FPMCU_RST_ODL */ PAD_CFG_GPO(GPP_C10, 1, DEEP), /* C11 : UART0_CTS# ==> FPMCU_INT */ - PAD_CFG_GPI_APIC(GPP_C11, 20K_PU, DEEP), + PAD_CFG_GPI_APIC(GPP_C11, 20K_PU, PLTRST), /* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* C13 : UART1_TXD ==> PCH_MEM_CONFIG[1] */