Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40363 )
Change subject: soc/intel/common/systemagent: Add new PCIEXBAR register LENGTH offset values
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Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40363/7/src/soc/intel/common/block/...
File src/soc/intel/common/block/systemagent/systemagent_early.c:
https://review.coreboot.org/c/coreboot/+/40363/7/src/soc/intel/common/block/...
PS7, Line 45: break;
yes valid point, i had some CL like this https://review.coreboot.org/c/coreboot/+/40337 […]
Well, we need something to indicate support in the chipset. Can we have a MMCONF_MAX_SIZE or something like that?
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