build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44699 )
Change subject: soc/mediatek/mt8192: Define DRAM registers and APIs
......................................................................
Patch Set 44:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44699/44/src/soc/mediatek/mt8192/in...
File src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h:
https://review.coreboot.org/c/coreboot/+/44699/44/src/soc/mediatek/mt8192/in...
PS44, Line 279: void dramc_write_leveling(const struct ddr_cali *cali, u8 dqs_final_delay[RANK_MAX][DQS_NUMBER]);
line over 96 characters
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