[coreboot-gerrit] Change in coreboot[master]: riscv: update delegate

[Xiang Wang (Code Review)]

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/28356

Change subject: riscv: update delegate
......................................................................

riscv: update delegate

PMP may trigger an access fault. PMP operations must be in m-mode. So access fault can't be delegate to s-mode.

Change-Id: If08220fdbb483ebf323f481ab0c7b012ac7a196c
Signed-off-by: Xiang Wang 
---
M src/arch/riscv/virtual_memory.c
1 file changed, 0 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/28356/1

diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c
index 3bee868..71e2ac9 100644
--- a/src/arch/riscv/virtual_memory.c
+++ b/src/arch/riscv/virtual_memory.c
@@ -26,11 +26,8 @@
  * the spec so for now we enumerate and set them all. */
 static int delegate = 0
    | (1 << CAUSE_MISALIGNED_FETCH)
-	| (1 << CAUSE_FETCH_ACCESS)
    | (1 << CAUSE_ILLEGAL_INSTRUCTION)
    | (1 << CAUSE_BREAKPOINT)
-	| (1 << CAUSE_LOAD_ACCESS)
-	| (1 << CAUSE_STORE_ACCESS)
    | (1 << CAUSE_USER_ECALL)
    | (1 << CAUSE_FETCH_PAGE_FAULT)
    | (1 << CAUSE_LOAD_PAGE_FAULT)