Attention is currently required from: Alexander Couzens, Michał Kopeć, Paul Menzel.
Maciej Pijanowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80609?usp=email )
Change subject: mb/lenovo: Add ThinkCentre M920q (Cannon Lake) ......................................................................
Patch Set 7:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80609/comment/b3163619_a0c1f4bb : PS6, Line 9: It may come with 8th or 9th Gen CPUs. : i5-8500T has been tested here.
Please do not break lines just because a sentence ends.
Ok, changed
File src/mainboard/lenovo/m920q/romstage.c:
https://review.coreboot.org/c/coreboot/+/80609/comment/4c60dc79_4629d51f : PS6, Line 13: .spd[0] = {
Platform only has 2 DIMMs
Correct, updated. This was mostly copied over from the reference board code, I think.
https://review.coreboot.org/c/coreboot/+/80609/comment/a04cfd01_bb7097e3 : PS6, Line 33: /* Rcomp target values for CFL-S, DDR4 and 2 DIMMs per channel */
There's 1 DIMM per channel here
Updated the comment. Do you suggest to change the values as well? I have looked into the Rcomp Info tool from Intel, and for CFL-S there is only entry for 2DPC.