[coreboot-gerrit] [L] Change in coreboot[main]: haswell NRI: Add write leveling

[Angel Pons (Code Review)]

Attention is currently required from: Arthur Heymans, Nico Huber.

Hello Arthur Heymans, Nico Huber, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/64197?usp=email

to look at the new patch set (#8).

Change subject: haswell NRI: Add write leveling
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haswell NRI: Add write leveling

Implement JEDEC write leveling, which is done in two steps. The first
step uses the JEDEC procedure to do "fine" write leveling, i.e. align
the DQS phase to the clock signal. The second step performs a regular
read-write test to correct "coarse" cycle errors.

Change-Id: I27678523fe22c38173a688e2a4751c259a20f009
Signed-off-by: Angel Pons 
---
M src/northbridge/intel/haswell/native_raminit/Makefile.mk
M src/northbridge/intel/haswell/native_raminit/raminit_main.c
M src/northbridge/intel/haswell/native_raminit/raminit_native.h
A src/northbridge/intel/haswell/native_raminit/train_jedec_write_leveling.c
M src/northbridge/intel/haswell/registers/mchbar.h
5 files changed, 595 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/64197/8