[coreboot-gerrit] Change in coreboot[master]: sb/intel/bd82x6x: Handle enabling of GbE

[Nico Huber (Code Review)]

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36902 )

Change subject: sb/intel/bd82x6x: Handle enabling of GbE
......................................................................

sb/intel/bd82x6x: Handle enabling of GbE

The integrated GbE port is toggled via the Backed-Up Control (BUC)
register. We already disable it according to the devicetree setting
but never enabled it. This could lead to the confusing situation
that it was disabled before (different build, vendor BIOS, etc.)
but shouldn't be anymore.

As we need a full reset after enabling GbE, do it in early PCH init.

Change-Id: I9db3d1923684b938d2c9f5b369b0953570c7fc15
Signed-off-by: Nico Huber 
---
M src/mainboard/intel/dcp847ske/early_southbridge.c
M src/southbridge/intel/bd82x6x/early_pch.c
M src/southbridge/intel/bd82x6x/pch.c
3 files changed, 28 insertions(+), 12 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/36902/1

diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c
index 1f76db8..34310a0 100644
--- a/src/mainboard/intel/dcp847ske/early_southbridge.c
+++ b/src/mainboard/intel/dcp847ske/early_southbridge.c
@@ -33,16 +33,6 @@
    /* Disable devices */
    RCBA32(FD) |= PCH_DISABLE_P2P;

-#if CONFIG(USE_NATIVE_RAMINIT)
-	/* Enable Gigabit Ethernet */
-	if (RCBA32(BUC) & PCH_DISABLE_GBE) {
-		RCBA32(BUC) &= ~PCH_DISABLE_GBE;
-		/* Datasheet says clearing the bit requires a reset after */
-		printk(BIOS_DEBUG, "Enabled gigabit ethernet, reset once.\n");
-		full_reset();
-	}
-#endif
-
    /* Set "mobile" bit in MCH (which makes sense layout-wise). */
    /* Note sure if this has any effect at all though. */
    MCHBAR32(0x0004) |= 0x00001000;
diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c
index 8ffb22e..9b6abba 100644
--- a/src/southbridge/intel/bd82x6x/early_pch.c
+++ b/src/southbridge/intel/bd82x6x/early_pch.c
@@ -16,6 +16,7 @@
 #include <device/mmio.h>
 #include <device/pci_ops.h>
 #include <arch/cbfs.h>
+#include <cf9_reset.h>
 #include <ip_checksum.h>
 #include <device/pci_def.h>
 #include <southbridge/intel/common/gpio.h>
@@ -253,6 +254,30 @@
    write_pmbase16(TCO1_CNT, 1 << 11);	/* halt timer */
 }

+static void pch_enable_gbe(void)
+{
+	uint16_t wanted_buc;
+
+	/* Don't do this in the bootblock, it might be RO. So one
+	   couldn't change the setting later in an updated romstage. */
+	if (ENV_BOOTBLOCK)
+		return;
+
+	struct device *const gbe = pcidev_on_root(0x19, 0);
+	if (gbe && gbe->enabled)
+		wanted_buc = RCBA16(BUC) & ~PCH_DISABLE_GBE;
+	else
+		wanted_buc = RCBA16(BUC) | PCH_DISABLE_GBE;
+
+	if (RCBA16(BUC) != wanted_buc) {
+		RCBA16(BUC) = wanted_buc;
+		/* Be double sure not to reset for naught. */
+		if (RCBA16(BUC) != wanted_buc)
+			return;
+		full_reset();
+	}
+}
+
 static void pch_enable_lpc_decode(void)
 {
    /*
@@ -292,7 +317,6 @@

void early_pch_init(void)
 {
-
    pch_enable_lpc_decode();

mainboard_pch_lpc_setup();
@@ -301,5 +325,7 @@

pch_generic_setup();

+	pch_enable_gbe();
+
    setup_pch_gpios(&mainboard_gpio_map);
 }
diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c
index de7fc36..00c29a8 100644
--- a/src/southbridge/intel/bd82x6x/pch.c
+++ b/src/southbridge/intel/bd82x6x/pch.c
@@ -169,7 +169,7 @@
    	RCBA32_OR(FD2, PCH_DISABLE_KT);
    	break;
    case PCI_DEVFN(25, 0): /* Gigabit Ethernet */
-		RCBA32_OR(BUC, PCH_DISABLE_GBE);
+		/* BUC is already handled in `early_pch.c`. */
    	break;
    case PCI_DEVFN(26, 0): /* EHCI #2 */
    	RCBA32_OR(FD, PCH_DISABLE_EHCI2);