Attention is currently required from: Felix Singer, Nico Huber, Frans Hendriks, Michael Niewöhner, Wim Vervoorn. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/57262 )
Change subject: skylake DDR4 boards: Set `CaVrefConfig` to 2 ......................................................................
skylake DDR4 boards: Set `CaVrefConfig` to 2
The `CaVrefConfig` FSP-M UPD describes how the on-die Vref generators are connected to the DRAM. With the exception of an early Skylake RVP board (which doesn't have coreboot support), mainboards using DDR3 or LPDDR3 memory should set `CaVrefConfig` to 0, whereas mainboards with DDR4 should set `CaVrefConfig` to 2. MRC uses this information during memory training, so it is important to use the correct value to avoid any issues, such as increased power usage, system instability or even boot failures.
However, several Skylake DDR4 mainboards don't set `CaVrefConfig` to 2. Although they can boot successfully, it's not optimal. For boards that set `DIMM_SPD_SIZE` to 512 (DDR4 SPD size), set `CaVrefConfig` to 2.
Change-Id: Idab77daff311584b3e3061e9bf107c2fc1b7bdf1 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/51nb/x210/romstage.c M src/mainboard/asrock/h110m/romstage.c M src/mainboard/clevo/kbl-u/variants/n13xwu/romstage.c M src/mainboard/facebook/monolith/romstage.c M src/mainboard/google/fizz/romstage.c M src/mainboard/kontron/bsl6/romstage.c M src/mainboard/purism/librem_skl/romstage.c M src/mainboard/supermicro/x11-lga1151-series/romstage.c 8 files changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/57262/1
diff --git a/src/mainboard/51nb/x210/romstage.c b/src/mainboard/51nb/x210/romstage.c index 38652b5..8a8fa4f 100644 --- a/src/mainboard/51nb/x210/romstage.c +++ b/src/mainboard/51nb/x210/romstage.c @@ -36,6 +36,7 @@ mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
mem_cfg->DqPinsInterleaved = TRUE; + mem_cfg->CaVrefConfig = 2; mem_cfg->MemorySpdDataLen = blk.len; mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0]; mem_cfg->MemorySpdPtr10 = (uintptr_t) blk.spd_array[1]; diff --git a/src/mainboard/asrock/h110m/romstage.c b/src/mainboard/asrock/h110m/romstage.c index f78aa30..aec7925 100644 --- a/src/mainboard/asrock/h110m/romstage.c +++ b/src/mainboard/asrock/h110m/romstage.c @@ -22,6 +22,7 @@ assert(sizeof(mem_cfg->RcompTarget) == sizeof(rcomp_targets));
mem_cfg->DqPinsInterleaved = 1; + mem_cfg->CaVrefConfig = 2; get_spd_smbus(&blk); mem_cfg->MemorySpdDataLen = blk.len; mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/romstage.c b/src/mainboard/clevo/kbl-u/variants/n13xwu/romstage.c index 4e9d57c..116d418 100644 --- a/src/mainboard/clevo/kbl-u/variants/n13xwu/romstage.c +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/romstage.c @@ -32,6 +32,7 @@ mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
mem_cfg->DqPinsInterleaved = TRUE; + mem_cfg->CaVrefConfig = 2; mem_cfg->MemorySpdDataLen = blk.len; mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; diff --git a/src/mainboard/facebook/monolith/romstage.c b/src/mainboard/facebook/monolith/romstage.c index 0a7a071..842724c 100644 --- a/src/mainboard/facebook/monolith/romstage.c +++ b/src/mainboard/facebook/monolith/romstage.c @@ -19,6 +19,7 @@ mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
mem_cfg->DqPinsInterleaved = 1; + mem_cfg->CaVrefConfig = 2; get_spd_smbus(&blk); mem_cfg->MemorySpdDataLen = blk.len; mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; diff --git a/src/mainboard/google/fizz/romstage.c b/src/mainboard/google/fizz/romstage.c index 85475e5..5df33da 100644 --- a/src/mainboard/google/fizz/romstage.c +++ b/src/mainboard/google/fizz/romstage.c @@ -27,6 +27,7 @@ .addr_map = { 0x50, 0x52, }, }; mem_cfg->DqPinsInterleaved = 1; + mem_cfg->CaVrefConfig = 2; get_spd_smbus(&blk); mem_cfg->MemorySpdDataLen = blk.len; mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; diff --git a/src/mainboard/kontron/bsl6/romstage.c b/src/mainboard/kontron/bsl6/romstage.c index f38734c..4689b3f 100644 --- a/src/mainboard/kontron/bsl6/romstage.c +++ b/src/mainboard/kontron/bsl6/romstage.c @@ -37,6 +37,7 @@ sizeof(memory_params->RcompTarget));
memory_params->DqPinsInterleaved = true; + mem_cfg->CaVrefConfig = 2;
const uint8_t ht = get_uint_option("hyper_threading", memory_params->HyperThreading); memory_params->HyperThreading = ht; diff --git a/src/mainboard/purism/librem_skl/romstage.c b/src/mainboard/purism/librem_skl/romstage.c index 1c90771..604db60 100644 --- a/src/mainboard/purism/librem_skl/romstage.c +++ b/src/mainboard/purism/librem_skl/romstage.c @@ -29,6 +29,7 @@ memcpy(mem_cfg->RcompTarget, rcomp_targets, sizeof(mem_cfg->RcompTarget));
mem_cfg->DqPinsInterleaved = TRUE; + mem_cfg->CaVrefConfig = 2; mem_cfg->MemorySpdDataLen = blk.len; mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0];
diff --git a/src/mainboard/supermicro/x11-lga1151-series/romstage.c b/src/mainboard/supermicro/x11-lga1151-series/romstage.c index 6763657..b4347d9 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/romstage.c +++ b/src/mainboard/supermicro/x11-lga1151-series/romstage.c @@ -13,6 +13,7 @@ };
mem_cfg->DqPinsInterleaved = 1; + mem_cfg->CaVrefConfig = 2; get_spd_smbus(&blk); mem_cfg->MemorySpdDataLen = blk.len; mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0];