[coreboot-gerrit] Change in coreboot[master]: soc/amd/common/block/update_microcode: Make ucode update more generic

[Fred Reitberger (Code Review)]

Fred Reitberger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63589 )

Change subject: soc/amd/common/block/update_microcode: Make ucode update more generic
......................................................................

soc/amd/common/block/update_microcode: Make ucode update more generic

Use microcode block headers to determine its size. This enables the use
case where different sized microcode blocks can be packaged together in
a single cbfs entry.

Change-Id: I84a2480cf8274d53ffdab7864135c1bf001241e6
Signed-off-by: Fred Reitberger 
---
M src/soc/amd/common/block/cpu/update_microcode.c
1 file changed, 27 insertions(+), 11 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/63589/1

diff --git a/src/soc/amd/common/block/cpu/update_microcode.c b/src/soc/amd/common/block/cpu/update_microcode.c
index 33b244d..c1d4138 100644
--- a/src/soc/amd/common/block/cpu/update_microcode.c
+++ b/src/soc/amd/common/block/cpu/update_microcode.c
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

#include <arch/cpu.h>
-#include <stdint.h>
+#include <types.h>
 #include <cpu/amd/microcode.h>
 #include <commonlib/helpers.h>
 #include <console/console.h>
@@ -12,13 +12,13 @@

#define CPU_MICROCODE_BLOB_NAME "cpu_microcode_blob.bin"

-_Static_assert(CONFIG_SOC_AMD_COMMON_BLOCK_UCODE_SIZE > 0,
-	       "SOC_AMD_COMMON_BLOCK_UCODE_SIZE is not set");
+#define CEZANNE_PROC_REV_ID	0xA500

-#define MPB_MAX_SIZE CONFIG_SOC_AMD_COMMON_BLOCK_UCODE_SIZE
-#define MPB_DATA_OFFSET 32
+#define UCODE_SIZE_3200		3200
+#define UCODE_SIZE_5568		5568
+#define MPB_MAX_SIZE UCODE_SIZE_5568  /* this needs to be the largest UCODE size*/

-struct microcode {
+struct microcode_hdr {
    uint32_t date_code;
    uint32_t patch_id;

@@ -34,12 +34,24 @@
    uint8_t chipset2_rev_id;

uint8_t reserved2[4];
+} __packed;

-	uint8_t m_patch_data[MPB_MAX_SIZE-MPB_DATA_OFFSET];
+struct microcode {
+	struct microcode_hdr hdr;
+	uint8_t m_patch_data[MPB_MAX_SIZE-sizeof(struct microcode_hdr)];
 } __packed;

_Static_assert(sizeof(struct microcode) == MPB_MAX_SIZE, "microcode size is invalid");

+static size_t get_ucode_size_for_proc_rev_id(uint16_t processor_rev_id)
+{
+	// currently, only cezanne has a different ucode size
+	if (processor_rev_id == CEZANNE_PROC_REV_ID)
+		return UCODE_SIZE_5568;
+
+	return UCODE_SIZE_3200;
+}
+
 static void apply_microcode_patch(const struct microcode *m)
 {
    uint32_t new_patch_id;
@@ -51,12 +63,12 @@
    wrmsr(MSR_PATCH_LOADER, msr);

printk(BIOS_DEBUG, "microcode: patch id to apply = 0x%08x\n",
-		m->patch_id);
+		m->hdr.patch_id);

msr = rdmsr(IA32_BIOS_SIGN_ID);
    new_patch_id = msr.lo;

-	if (new_patch_id == m->patch_id)
+	if (new_patch_id == m->hdr.patch_id)
    	printk(BIOS_INFO, "microcode: being updated to patch id = 0x%08x succeeded\n",
    		new_patch_id);
    else
@@ -75,10 +87,14 @@
 {
    uint16_t equivalent_processor_rev_id = get_equivalent_processor_rev_id();
    const struct microcode *m;
+	uintptr_t addr = (uintptr_t)ucode;
+	const struct microcode *end = (const struct microcode *)((uintptr_t)ucode + ucode_len);

-	for (m = ucode; m < ucode + ucode_len / MPB_MAX_SIZE; m++) {
-		if (m->processor_rev_id == equivalent_processor_rev_id)
+	for (m = ucode; m < end; ) {
+		if (m->hdr.processor_rev_id == equivalent_processor_rev_id)
    		return m;
+		addr += get_ucode_size_for_proc_rev_id(m->hdr.processor_rev_id);
+		m = (const struct microcode*)addr;
    }

printk(BIOS_WARNING, "Failed to find microcode for processor rev: %hx.\n",