Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39285 )
Change subject: mb/intel/dedede: Add Audio support ......................................................................
mb/intel/dedede: Add Audio support
1. Configure Audio GPIOs. 2. Set i2c4 configuration.
Signed-off-by: Pandya, Varshit B varshit.b.pandya@intel.com Signed-off-by: Yong Zhi yong.zhi@intel.com Change-Id: Ic0516c7a8fee79ce17343a7f42895d6ef534fec9 --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/gpio.c 2 files changed, 29 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/39285/1
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index e4750ec..4b372b2 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -150,7 +150,13 @@ device pci 16.4 off end # HECI 3 device pci 16.5 off end # HECI 4 device pci 17.0 off end # SATA - device pci 19.0 on end # I2C 4 + device pci 19.0 on + chip drivers/generic/max98357a + register "hid" = ""MX98360A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)" + device generic 0 on end + end + end # I2C #4 device pci 19.1 off end # I2C 5 device pci 19.2 on end # UART 2 device pci 1a.0 on end # eMMC diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 8049040..169772b 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -13,6 +13,19 @@
/* Pad configuration in ramstage*/ static const struct pad_config gpio_table[] = { + /* R0 : I2S_HP_BCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* R1 : I2S_HP_LRCK */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* R2 : I2S_HP_AUDIO */ + PAD_CFG_NF(GPP_R2, NONE, DEEP, NF2), + /* R3 : I2S_HP_MIC */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + /* R6 : I2S_SPK_LRCK */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF1), + /* R7 : I2S_SPK_AUDIO */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF1), + /* GPP_A0 thru GPP_A6 come configured out of reset, do not touch */ /* A0 : ESPI_IO0 */ /* A1 : ESPI_IO1 */ @@ -72,6 +85,13 @@ /* C23 : UART2_CTS_N */ PAD_NC(GPP_C23, DN_20K),
+ /* D16 : HP_INT_ODL*/ + AD_CFG_GPI_INT(GPP_D16, NONE, PLTRST, EDGE_BOTH), + /* D17 : EN_SPK */ + PAD_CFG_GPO(GPP_D17, 1, PLTRST), + /* D18 : I2S_MCLK */ + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), + /* F7 : EMMC_CMD */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), /* F8 : EMMC_DATA0 */ @@ -126,6 +146,8 @@ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* H9 : AP_I2C_AUDIO_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + /* H15 : I2S_SPK_BCLK */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), };
/* Early pad configuration in bootblock */