[coreboot-gerrit] Change in ...coreboot[master]: nb/intel/sandybridge: Reserve CAR region with !NATIVE_RAMINIT

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31150 )

Change subject: nb/intel/sandybridge: Reserve CAR region with !NATIVE_RAMINIT
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Patch Set 3:
> Patch Set 3:
> > Patch Set 3:
> >
> > kmalkki: so test on HSW, BDW, BYT then? Assuming IVB is covered by this already
>
> Well I am hoping this would have been improved for haswell already. I don't seem to get or ask the correct questions to get this answered from Google. Mostly because these are 5 years old already.

I can have a look at the output data pointer on haswell to see what it's doing, but a quick look at the binary did not find weird pointers outside the DCACHE_RAM_MRC_VAR region.

The blobs repo has multiple binaries for sandy/ivy but we generally end up using systemagent-r6.bin. Do we know the other ones have the same heap? (also do we care?)