Hello Marshall Dawson, Marshall Dawson,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/40295
to review the following change.
Change subject: soc/amd/common/psp: Add SmmInfo command ......................................................................
soc/amd/common/psp: Add SmmInfo command
Implement the MboxBiosCmdSmmInfo function to inform the PSP of the soc's SMM configuration. Once the BootDone command is sent, the PSP only responds to commands where the buffer is in SM memory.
Set aside a region for the core-to-PSP command buffer and the PSP-to-core mailbox. Also add an SMM flag, which the PSP expects to read as non-zero during an SMI.
The soc should call the new function only from an SMI handler. Add calls to soc functions for the soc to populate the trigger info and register info (v2 only).
Change-Id: I10088a53e786db788740e4b388650641339dae75 Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com --- M src/soc/amd/common/block/include/amdblocks/psp.h M src/soc/amd/common/block/psp/psp.c M src/soc/amd/common/block/psp/psp_def.h 3 files changed, 147 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/40295/1
diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h index 53946fb..c084bb1 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp.h +++ b/src/soc/amd/common/block/include/amdblocks/psp.h @@ -7,6 +7,39 @@ /* Get the mailbox base address - specific to family of device. */ void *soc_get_mbox_address(void);
+#define SMM_TRIGGER_IO 0 +#define SMM_TRIGGER_MEM 1 + +#define SMM_TRIGGER_BYTE 0 +#define SMM_TRIGGER_WORD 1 +#define SMM_TRIGGER_DWORD 2 + +struct smm_trigger_info { + uint64_t address; /* Memory or IO address */ + uint32_t address_type; /* 0=I/O, 1=memory */ + uint32_t value_width; /* 0=byte, 1=word, 2=qword */ + uint32_t value_and_mask; + uint32_t value_or_mask; +} __packed; + +struct smm_register { + uint64_t address; /* Memory or IO address */ + uint32_t address_type; /* 0=I/O, 1=memory */ + uint32_t value_width; /* 0=byte, 1=word, 2=qword */ + uint32_t reg_bit_mask; + uint32_t expect_value; +} __packed; + +struct smm_register_info { + struct smm_register smi_enb; + struct smm_register eos; + struct smm_register psp_smi_en; + struct smm_register reserved[5]; +} __packed; + +void soc_fill_smm_trig_info(struct smm_trigger_info *trig); +void soc_fill_smm_reg_info(struct smm_register_info *reg); /* v2 only */ + /* BIOS-to-PSP functions return 0 if successful, else negative value */ #define PSPSTS_SUCCESS 0 #define PSPSTS_NOBASE 1 @@ -22,6 +55,8 @@
int psp_notify_dram(void);
+int psp_notify_smm(void); + /* * type: identical to the corresponding PSP command, e.g. pass * MBOX_BIOS_CMD_SMU_FW2 to load SMU FW2 blob. diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c index 77517c0..9baabf7 100644 --- a/src/soc/amd/common/block/psp/psp.c +++ b/src/soc/amd/common/block/psp/psp.c @@ -3,11 +3,13 @@
#include <device/mmio.h> #include <cpu/x86/msr.h> +#include <cpu/amd/msr.h> #include <cbfs.h> #include <region_file.h> #include <timer.h> #include <device/pci_def.h> #include <bootstate.h> +#include <rules.h> #include <console/console.h> #include <device/pci_ops.h> #include <amdblocks/psp.h> @@ -15,6 +17,33 @@ #include <soc/northbridge.h> #include "psp_def.h"
+struct _c2p_buffer { + u8 buffer[C2P_BUFFER_MAXSIZE]; +} __attribute__((aligned(32))); + +struct _p2c_buffer { + u8 buffer[P2C_BUFFER_MAXSIZE]; +} __attribute__((aligned(32))); + +static struct _p2c_buffer p2c_buffer; +static struct _c2p_buffer c2p_buffer; + +static uint32_t smm_flag; /* Non-zero for SMM, clear when not */ + +static void set_smm_flag(void) +{ + if (!(ENV_SMM)) + return; + smm_flag = 1; +} + +static void clear_smm_flag(void) +{ + if (!(ENV_SMM)) + return; + smm_flag = 0; +} + static const char *psp_status_nobase = "error: PSP BAR3 not assigned"; static const char *psp_status_halted = "error: PSP in halted state"; static const char *psp_status_recovery = "error: PSP recovery required"; @@ -111,13 +140,18 @@ if (v1_wait_command(mbox)) return -PSPSTS_CMD_TIMEOUT;
- /* set address of command-response buffer and write command register */ + /* set smm flag, address of command-response buffer and write command */ + set_smm_flag(); v1_wr_mbox_cmd_resp(mbox, buffer); v1_wr_mbox_cmd(mbox, command);
/* PSP clears command register when complete */ - if (v1_wait_command(mbox)) + if (v1_wait_command(mbox)) { + clear_smm_flag(); return -PSPSTS_CMD_TIMEOUT; + } + + clear_smm_flag();
/* check delivery status */ if (v1_rd_mbox_sts(mbox) & (PSPV1_STATUS_ERROR | PSPV1_STATUS_TERMINATED)) @@ -192,15 +226,20 @@ if (v2_wait_command(mbox, true)) return -PSPSTS_CMD_TIMEOUT;
- /* set address of command-response buffer and write command register */ + /* set smm flag, address of command-response buffer and write command */ + set_smm_flag(); v2_wr_mbox_cmd_resp(mbox, buffer); v2_wr_mbox_cmd(mbox, command);
/* PSP clears command register when complete. All commands except * SxInfo set the Ready bit. */ if (v2_wait_command(mbox, - command == MBOX_BIOS_CMD_SX_INFO ? false : true)) + command == MBOX_BIOS_CMD_SX_INFO ? false : true)) { + clear_smm_flag(); return -PSPSTS_CMD_TIMEOUT; + } + + clear_smm_flag();
/* check delivery status */ if (v2_rd_mbox_sts(mbox)) @@ -282,6 +321,48 @@ print_cmd_status(cmd_status, &buffer); }
+int psp_notify_smm(void) +{ + msr_t msr; + int cmd_status; + struct mbox_cmd_smm_info_buffer buffer = { + .header = { + .size = sizeof(buffer) + } + }; + + if (!(ENV_SMM)) { + printk (BIOS_ERR, "PSP: Error, cannot send SMM info from outside SMM\n"); + return PSPSTS_UNSUPPORTED; + } + + msr = rdmsr(SMM_ADDR_MSR); + buffer.req.smm_base = ((uint64_t)msr.hi << 32) | msr.lo; + msr = rdmsr(SMM_MASK_MSR); + msr.lo &= 0xfffff000; + buffer.req.smm_mask = ((uint64_t)msr.hi << 32) | msr.lo; + + soc_fill_smm_trig_info(&buffer.req.smm_trig_info); +#if (CONFIG(SOC_AMD_COMMON_BLOCK_PSP_GEN2)) + soc_fill_smm_reg_info(&buffer.req.smm_reg_info); +#endif + + buffer.req.psp_smm_data_region = (uintptr_t)p2c_buffer.buffer; + buffer.req.psp_smm_data_length = sizeof(p2c_buffer); + + buffer.req.psp_mbox_smm_buffer_address = (uintptr_t)c2p_buffer.buffer; + buffer.req.psp_mbox_smm_flag_address = (uintptr_t)&smm_flag; + + printk(BIOS_DEBUG, "PSP: Notify SMM info... "); + + cmd_status = send_psp_command(MBOX_BIOS_CMD_SMM_INFO, &buffer); + + /* buffer's status shouldn't change but report it if it does */ + print_cmd_status(cmd_status, (struct mbox_default_buffer *)&buffer); + + return cmd_status; +} + /* * Tell the PSP to load a firmware blob from a location in the BIOS image. */ diff --git a/src/soc/amd/common/block/psp/psp_def.h b/src/soc/amd/common/block/psp/psp_def.h index dd0c907..f101fb3 100644 --- a/src/soc/amd/common/block/psp/psp_def.h +++ b/src/soc/amd/common/block/psp/psp_def.h @@ -6,6 +6,7 @@
#include <types.h> #include <commonlib/helpers.h> +#include <amdblocks/psp.h>
/* x86 to PSP commands */ #define MBOX_BIOS_CMD_DRAM_INFO 0x01 @@ -81,6 +82,24 @@ struct mbox_buffer_header header; } __attribute__((packed, aligned(32)));
+struct smm_req_buffer { + uint64_t smm_base; /* TSEG base */ + uint64_t smm_mask; /* TSEG mask */ + uint64_t psp_smm_data_region; /* PSP region in SMM space */ + uint64_t psp_smm_data_length; /* PSP region length in SMM space */ + struct smm_trigger_info smm_trig_info; +#if CONFIG(SOC_AMD_COMMON_BLOCK_PSP_GEN2) + struct smm_register_info smm_reg_info; +#endif + uint64_t psp_mbox_smm_buffer_address; + uint64_t psp_mbox_smm_flag_address; +} __packed; + +struct mbox_cmd_smm_info_buffer { + struct mbox_buffer_header header; + struct smm_req_buffer req; +} __attribute__((packed, aligned(32))); + struct mbox_cmd_sx_info_buffer { struct mbox_buffer_header header; u8 sleep_type; @@ -89,4 +108,12 @@ #define PSP_INIT_TIMEOUT 10000 /* 10 seconds */ #define PSP_CMD_TIMEOUT 1000 /* 1 second */
+#if ENV_SMM +#define C2P_BUFFER_MAXSIZE 0xc00 /* Core-to-PSP buffer */ +#define P2C_BUFFER_MAXSIZE 0xc00 /* PSP-to-core buffer */ +#else +#define C2P_BUFFER_MAXSIZE 0 +#define P2C_BUFFER_MAXSIZE 0 +#endif + #endif /* __AMD_PSP_DEF_H__ */