Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79832?usp=email )
Change subject: src/soc/amd/glinda: Update the PCIE MMCONFIG base address and size ......................................................................
src/soc/amd/glinda: Update the PCIE MMCONFIG base address and size
The PCIE MMCONFIG base address value and size is updated correctly to access the PCIE config space registers.
TEST=Verified that PCIE enumeration takes place in boot log and config space registers are accessible.
Change-Id: Ifa8377df7a2973a88d414c217b5ed114c8ae5cc3 Signed-off-by: Anand Vaikar a.vaikar2021@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/79832 Reviewed-by: Felix Held felix-coreboot@felixheld.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/amd/glinda/Kconfig 1 file changed, 2 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved
diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig index ac0c96b..b976048 100644 --- a/src/soc/amd/glinda/Kconfig +++ b/src/soc/amd/glinda/Kconfig @@ -234,10 +234,10 @@ default "apu/amdfw"
config ECAM_MMCONF_BASE_ADDRESS - default 0xF8000000 + default 0xE0000000
config ECAM_MMCONF_BUS_NUMBER - default 64 + default 256
config MAX_CPUS int