[coreboot-gerrit] Change in coreboot[master]: soc/intel/jsl: Add DisableExternalVnnVcc1p05BypassMode config

[Kane Chen (Code Review)]

Attention is currently required from: Paul Menzel, Patrick Rudolph.
Kane Chen has uploaded a new patch set (#10) to the change originally created by Simon Yang. ( https://review.coreboot.org/c/coreboot/+/55744 )

Change subject: soc/intel/jsl: Add DisableExternalVnnVcc1p05BypassMode config
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soc/intel/jsl: Add DisableExternalVnnVcc1p05BypassMode config

This dev tree config controls the Vnn/Vcc1P05 bypass mode for Jasperlake.

BUG=b:191691430
BRANCH=dedede
TEST=Build fw and confirm FSP setting are set properly by log

Signed-off-by: Simon Yang 
Change-Id: I10bc203d3fed32ab65f325978426b7d0fca6f392
---
M src/soc/intel/jasperlake/chip.h
M src/soc/intel/jasperlake/fsp_params.c
2 files changed, 26 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/55744/10