[coreboot-gerrit] [S] Change in coreboot[master]: soc/intel/cmn: Clear interrupt status after HECI-1 has been received

[Johnny Lin (Code Review)]

Attention is currently required from: Arthur Heymans, Marc Jones, Wonkyu Kim, Subrata Banik, Jonathan Zhang, Daocheng Bu, Rizwan Qureshi, Jingle Hsu, Sridhar Siricilla, Shuming Chu (Shuming), Shelly Chang.

Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66579 )

Change subject: soc/intel/cmn: Clear interrupt status after HECI-1 has been received
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Patch Set 4:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/66579/comment/8fe0be4c_749ab08a 
PS4, Line 15:  get_me_fw_version
> Thanks Johnny for clarification. […]

My test result:
The interrupt status is not set before and after line 542 clear_int();
The interrupt status is set right before line 572 return CSE_TX_RX_SUCCESS;

File src/soc/intel/common/block/cse/cse.c:

https://review.coreboot.org/c/coreboot/+/66579/comment/95163074_cb99689d 
PS4, Line 542: 	clear_int();
> Is this too early in your platform? Can you check interrupt status before this code clears?

Yes it's too early.