[coreboot-gerrit] Change in ...coreboot[master]: mb/google/poppy/vr/atlas: Add a W/A for Samsung memory init error

[Gaggery Tsai (Code Review)]

Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32695

Change subject: mb/google/poppy/vr/atlas: Add a W/A for Samsung memory init error
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mb/google/poppy/vr/atlas: Add a W/A for Samsung memory init error

This patch adds a workaround for Samsung C-die 2G/4G memory chips.
For unknown reasons, some boards with Samsung LP3 memory chips
could not pass early CS/CMD training. MRC has to change the
granularity from 16 ticks to 8 ticks, which implies bad margin
with this memory chip. Another way is to enhance the drive
strength for CS. This patch is to enhance the drive strength for CS.
Root cause needs to be further investigated with memory vendor.

BUG=b:131177542
BRANCH=None
TEST=USE=fw_debug emerge-atlas chromeos-mrc coreboot chromeos-bootimage
     & check the MRC log to ensure correct Rcomp values are passed to
     MRC. Tested with board ID #8 and #11.

Change-Id: I9ea3ceda8dc8bf781063d3c16c7c2d9b44e5ddd6
Signed-off-by: Gaggery Tsai 
---
M src/mainboard/google/poppy/variants/atlas/memory.c
1 file changed, 12 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/32695/1

diff --git a/src/mainboard/google/poppy/variants/atlas/memory.c b/src/mainboard/google/poppy/variants/atlas/memory.c
index 0b34e72..7b0d17a 100644
--- a/src/mainboard/google/poppy/variants/atlas/memory.c
+++ b/src/mainboard/google/poppy/variants/atlas/memory.c
@@ -13,8 +13,11 @@
  * GNU General Public License for more details.
  */

+#include <assert.h>
 #include <baseboard/variants.h>

+#define SAMSUNG_C_DIE_2G	10
+#define SAMSUNG_C_DIE_4G	11
 /* DQ byte map */
 static const u8 dq_map[][12] = {
    { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
@@ -34,9 +37,12 @@

/* Rcomp target */
 static const u16 rcomp_target[] = { 100, 40, 40, 23, 40 };
+static const u16 rcomp_target_samsung_c_die[] = { 100, 40, 40, 18, 40 };

void variant_memory_params(struct memory_params *p)
 {
+	int spd_index;
+
    p->type = MEMORY_LPDDR3;
    p->dq_map = dq_map;
    p->dq_map_size = sizeof(dq_map);
@@ -44,6 +50,11 @@
    p->dqs_map_size = sizeof(dqs_map);
    p->rcomp_resistor = rcomp_resistor;
    p->rcomp_resistor_size = sizeof(rcomp_resistor);
-	p->rcomp_target = rcomp_target;
+	spd_index = variant_memory_sku();
+	assert(spd_index >= 0);
+	if (spd_index == SAMSUNG_C_DIE_2G || spd_index == SAMSUNG_C_DIE_4G)
+		p->rcomp_target = rcomp_target_samsung_c_die;
+	else
+		p->rcomp_target = rcomp_target;
    p->rcomp_target_size = sizeof(rcomp_target);
 }