Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/29470
Change subject: src/mainboard/portwell/m107: Do initial mainboard commit ......................................................................
src/mainboard/portwell/m107: Do initial mainboard commit
No support for Portwell PQ7-M107. Create (braswell) board based on Intel Strago.
BUG=N/A TEST=Portwell PQ7-M107
Change-Id: I7d3173fdcf881f894a75cd9798ba173b425d4e62 Signed-off-by: Frans Hendriks fhendriks@eltan.com --- A src/mainboard/portwell/Kconfig A src/mainboard/portwell/Kconfig.name A src/mainboard/portwell/m107/Kconfig A src/mainboard/portwell/m107/Kconfig.name A src/mainboard/portwell/m107/Makefile.inc A src/mainboard/portwell/m107/acpi/dptf.asl A src/mainboard/portwell/m107/acpi/ec.asl A src/mainboard/portwell/m107/acpi/mainboard.asl A src/mainboard/portwell/m107/acpi/sleepstates.asl A src/mainboard/portwell/m107/acpi/superio.asl A src/mainboard/portwell/m107/acpi_tables.c A src/mainboard/portwell/m107/board_info.txt A src/mainboard/portwell/m107/cmos.layout A src/mainboard/portwell/m107/com_init.c A src/mainboard/portwell/m107/devicetree.cb A src/mainboard/portwell/m107/dsdt.asl A src/mainboard/portwell/m107/fadt.c A src/mainboard/portwell/m107/gpio.c A src/mainboard/portwell/m107/hda_verb.c A src/mainboard/portwell/m107/irqroute.c A src/mainboard/portwell/m107/irqroute.h A src/mainboard/portwell/m107/mainboard.c A src/mainboard/portwell/m107/onboard.h A src/mainboard/portwell/m107/romstage.c A src/mainboard/portwell/m107/smihandler.c A src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex A src/mainboard/portwell/m107/w25q64.c 27 files changed, 1,613 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/29470/1
diff --git a/src/mainboard/portwell/Kconfig b/src/mainboard/portwell/Kconfig new file mode 100644 index 0000000..78e5037 --- /dev/null +++ b/src/mainboard/portwell/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_PORTWELL + +choice + prompt "Mainboard model" + +source "src/mainboard/portwell/*/Kconfig.name" + +endchoice + +source "src/mainboard/portwell/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "Portwell" + +endif # VENDOR_PORTWELL diff --git a/src/mainboard/portwell/Kconfig.name b/src/mainboard/portwell/Kconfig.name new file mode 100644 index 0000000..12240ed --- /dev/null +++ b/src/mainboard/portwell/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_PORTWELL + bool "Portwell" diff --git a/src/mainboard/portwell/m107/Kconfig b/src/mainboard/portwell/m107/Kconfig new file mode 100644 index 0000000..f1cdd82 --- /dev/null +++ b/src/mainboard/portwell/m107/Kconfig @@ -0,0 +1,75 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. +## Copyright (C) 2018 Eltan B.V. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_PORTWELL_M107 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select MAINBOARD_HAS_LPC_TPM + select SOC_INTEL_BRASWELL + select PCIEXP_L1_SUB_STATE + select CACHE_MRC_SETTINGS + +config DYNAMIC_VNN_SUPPORT + bool "Enables support for Dynamic VNN" + default n + +config MAINBOARD_DIR + string + default portwell/m107 + +config MAINBOARD_PART_NUMBER + string + default "PQ7-M107" + +config MAINBOARD_SPD0_FILE_NAME + string + default "spd0.bin" + +config CBFS_SIZE + hex + default 0x00800000 + +config CPU_MICROCODE_CBFS_LEN + hex + default 0x10C00 + help + This should be updated when the microcode patch changes. + +config CPU_MICROCODE_CBFS_LOC + hex + default 0xfffee000 + +config ROM_SIZE + hex + default 0x800000 + +config MRC_SETTINGS_CACHE_SIZE + hex + default 0x08000 + +config SPI_FLASH_INCLUDE_ALL_DRIVERS + bool + default n + +config SPI_FLASH_WINBOND + bool + default y + +endif # BOARD_PORTWELL_M107 diff --git a/src/mainboard/portwell/m107/Kconfig.name b/src/mainboard/portwell/m107/Kconfig.name new file mode 100644 index 0000000..eca9589 --- /dev/null +++ b/src/mainboard/portwell/m107/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_PORTWELL_M107 + bool "PQ7-M107" diff --git a/src/mainboard/portwell/m107/Makefile.inc b/src/mainboard/portwell/m107/Makefile.inc new file mode 100644 index 0000000..c87e8ec --- /dev/null +++ b/src/mainboard/portwell/m107/Makefile.inc @@ -0,0 +1,44 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2015 Intel Corp. +## Copyright (C) 2018 Eltan B.V. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-y += gpio.c +ramstage-y += irqroute.c +ramstage-y += hda_verb.c +ramstage-y += w25q64.c + +romstage-y += com_init.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +## +## Memory SPD for on-board memory +## +SPD0_BIN = $(obj)/sp0.bin +SPD0_SOURCE = spd/SAMSUNG_K4B8G1646D-MYKO +SPD0_DEPS := $(top)/src/mainboard/$(MAINBOARDDIR)/$(SPD0_SOURCE).spd.hex +# Include spd 0 rom data +$(SPD0_BIN): $(SPD0_DEPS) $(top)/src/mainboard/$(MAINBOARDDIR)/Makefile.inc + echo " CREATE SPD $@" + for f in $(SPD0_DEPS); \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '%o' 0x$$c); \ + done; \ + done > $@ +cbfs-files-y += $(CONFIG_MAINBOARD_SPD0_FILE_NAME) +$(CONFIG_MAINBOARD_SPD0_FILE_NAME)-file := $(SPD0_BIN) +$(CONFIG_MAINBOARD_SPD0_FILE_NAME)-type := spd + diff --git a/src/mainboard/portwell/m107/acpi/dptf.asl b/src/mainboard/portwell/m107/acpi/dptf.asl new file mode 100644 index 0000000..564237a --- /dev/null +++ b/src/mainboard/portwell/m107/acpi/dptf.asl @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/* Mainboard specific _PDL is 1GHz */ +Name (MPDL, 8) + +Name (DTRT, Package () { +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 2000, /* PowerLimitMinimum */ + 6200, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 8000, /* PowerLimitMinimum */ + 8000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) + +/* Include DPTF */ +#include <acpi/dptf/dptf.asl> diff --git a/src/mainboard/portwell/m107/acpi/ec.asl b/src/mainboard/portwell/m107/acpi/ec.asl new file mode 100644 index 0000000..3c9d818 --- /dev/null +++ b/src/mainboard/portwell/m107/acpi/ec.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ diff --git a/src/mainboard/portwell/m107/acpi/mainboard.asl b/src/mainboard/portwell/m107/acpi/mainboard.asl new file mode 100644 index 0000000..bc121da --- /dev/null +++ b/src/mainboard/portwell/m107/acpi/mainboard.asl @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (_SB) +{ + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + Name (_UID, 1) + } +} + +Scope (_SB.PCI0.LPEA) +{ + Name (GBUF, ResourceTemplate () + { + }) +} diff --git a/src/mainboard/portwell/m107/acpi/sleepstates.asl b/src/mainboard/portwell/m107/acpi/sleepstates.asl new file mode 100644 index 0000000..428fda2 --- /dev/null +++ b/src/mainboard/portwell/m107/acpi/sleepstates.asl @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Name(_S0, Package(){0x0,0x0,0x0,0x0}) +Name(_S4, Package(){0x6,0x6,0x0,0x0}) +Name(_S5, Package(){0x7,0x7,0x0,0x0}) diff --git a/src/mainboard/portwell/m107/acpi/superio.asl b/src/mainboard/portwell/m107/acpi/superio.asl new file mode 100644 index 0000000..712f36a --- /dev/null +++ b/src/mainboard/portwell/m107/acpi/superio.asl @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* mainboard configuration */ +#include "onboard.h" + + Device (COM1) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 1) + Name (_ADR, 0) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x03F8, 0x3F8, 0x08, 0x08) + IO (Decode16,0x6E,0x6E,0x1,0x02) + IRQNoFlags () {4} + }) + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0, 0) { + IO (Decode16, 0x03F8, 0x3F8, 0x08, 0x08) + IO (Decode16,0x6E,0x6E,0x1,0x02) + IRQNoFlags () {4} + } + EndDependentFn () + }) + } + diff --git a/src/mainboard/portwell/m107/acpi_tables.c b/src/mainboard/portwell/m107/acpi_tables.c new file mode 100644 index 0000000..15c955a --- /dev/null +++ b/src/mainboard/portwell/m107/acpi_tables.c @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <soc/acpi.h> +#include <soc/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + acpi_init_gnvs(gnvs); + + /* Enable USB ports in S3 */ + gnvs->s3u0 = 1; + gnvs->s3u1 = 1; + + /* Disable USB ports in S5 */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* Disable DPTF */ + gnvs->dpte = 0; + + /* PMIC is configured in I2C1, hide it for the OS */ + gnvs->dev.lpss_en[LPSS_NVS_I2C2] = 0; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + current = acpi_madt_irq_overrides(current); + + return current; +} diff --git a/src/mainboard/portwell/m107/board_info.txt b/src/mainboard/portwell/m107/board_info.txt new file mode 100644 index 0000000..d11212a --- /dev/null +++ b/src/mainboard/portwell/m107/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Portwell +Board name: PQ7-M107 +Category: misc +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/portwell/m107/cmos.layout b/src/mainboard/portwell/m107/cmos.layout new file mode 100644 index 0000000..3f953a8 --- /dev/null +++ b/src/mainboard/portwell/m107/cmos.layout @@ -0,0 +1,124 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2015 Intel Corp. +## Copyright (C) 2018 Eltan B.V. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#416 480 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/portwell/m107/com_init.c b/src/mainboard/portwell/m107/com_init.c new file mode 100644 index 0000000..a2bece9 --- /dev/null +++ b/src/mainboard/portwell/m107/com_init.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/romstage.h> +#include "onboard.h" + +#define SERIAL_DEV PNP_DEV(ITE8528_CMD_PORT, 1) // ITE8528 UART1 + +void car_mainboard_pre_console_init(void) +{ + if (!IS_ENABLED(CONFIG_ENABLE_BUILTIN_COM1)) { + /* Enable the serial port inside the EC */ + pnp_set_logical_device(SERIAL_DEV); + pnp_set_enable(SERIAL_DEV, 1); + } +} diff --git a/src/mainboard/portwell/m107/devicetree.cb b/src/mainboard/portwell/m107/devicetree.cb new file mode 100644 index 0000000..a6c4653 --- /dev/null +++ b/src/mainboard/portwell/m107/devicetree.cb @@ -0,0 +1,127 @@ +chip soc/intel/braswell + + ############################################################ + # Set the parameters for MemoryInit + ############################################################ + + register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB + + register "PcdMrcInitMmioSize" = "0x0800" + register "PcdMrcInitSpdAddr1" = "0xa0" + register "PcdMrcInitSpdAddr2" = "0xa2" + register "PcdIgdDvmt50PreAlloc" = "1" + register "PcdApertureSize" = "2" + register "PcdGttSize" = "1" + register "PcdDvfsEnable" = "0" + register "PcdCaMirrorEn" = "1" + + ############################################################ + # Set the parameters for SiliconInit + ############################################################ + + register "PcdSdcardMode" = "0" + register "PcdEnableHsuart0" = "0" + register "PcdEnableHsuart1" = "0" + register "PcdEnableAzalia" = "1" + register "PcdEnableXhci" = "1" + register "PcdEnableLpe" = "1" + register "PcdEnableDma0" = "0" + register "PcdEnableDma1" = "0" + register "PcdEnableI2C0" = "0" + register "PcdEnableI2C1" = "0" + register "PcdEnableI2C2" = "0" + register "PcdEnableI2C3" = "0" + register "PcdEnableI2C4" = "0" + register "PcdEnableI2C5" = "0" + register "PcdEnableI2C6" = "0" + register "PunitPwrConfigDisable" = "0" # Enable SVID + register "ChvSvidConfig" = "1" + register "PcdEmmcMode" = "PCH_PCI_MODE" + register "PcdUsb3ClkSsc" = "1" + register "PcdDispClkSsc" = "1" + register "PcdSataClkSsc" = "1" + register "PcdEnableSata" = "0" # Disable SATA + register "Usb2Port0PerPortPeTxiSet" = "7" + register "Usb2Port0PerPortTxiSet" = "5" + register "Usb2Port0IUsbTxEmphasisEn" = "2" + register "Usb2Port0PerPortTxPeHalf" = "1" + register "Usb2Port1PerPortPeTxiSet" = "7" + register "Usb2Port1PerPortTxiSet" = "3" + register "Usb2Port1IUsbTxEmphasisEn" = "2" + register "Usb2Port1PerPortTxPeHalf" = "1" + register "Usb2Port2PerPortPeTxiSet" = "7" + register "Usb2Port2PerPortTxiSet" = "3" + register "Usb2Port2IUsbTxEmphasisEn" = "2" + register "Usb2Port2PerPortTxPeHalf" = "1" + register "Usb2Port3PerPortPeTxiSet" = "7" + register "Usb2Port3PerPortTxiSet" = "3" + register "Usb2Port3IUsbTxEmphasisEn" = "2" + register "Usb2Port3PerPortTxPeHalf" = "1" + register "Usb2Port4PerPortPeTxiSet" = "7" + register "Usb2Port4PerPortTxiSet" = "3" + register "Usb2Port4IUsbTxEmphasisEn" = "2" + register "Usb2Port4PerPortTxPeHalf" = "1" + register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a" + register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" + register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" + register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" + register "PcdSataInterfaceSpeed" = "3" + register "PcdPchSsicEnable" = "1" + register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM + register "PMIC_I2CBus" = "0" + register "ISPEnable" = "0" # Disable IUNIT + register "ISPPciDevConfig" = "3" + register "PcdSdDetectChk" = "0" # Disable SD card detect + register "DptfDisable" = "1" + + # LPE audio codec settings + register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock + + # Enable devices in PCI mode + register "lpss_acpi_mode" = "0" + register "emmc_acpi_mode" = "0" + register "sd_acpi_mode" = "0" + register "lpe_acpi_mode" = "0" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # 8086 2280 - SoC router + device pci 02.0 on end # 8086 22B1 - GFX + device pci 0b.0 on end # 8086 22DC - PUNIT/DPTF + device pci 10.0 on end # 8086 2294 - MMC Port + device pci 12.0 on end # 8086 0F16 - SD Port + device pci 14.0 on end # 8086 22b5 - USB XHCI - Only 1 USB controller at a time + device pci 18.0 off end # 8086 22c0 - SIO - DMA + device pci 18.1 off end # 8086 22c1 - I2C Port 1 + device pci 18.2 off end # 8086 22c2 - I2C Port 2 + device pci 18.3 off end # 8086 22c3 - I2C Port 3 + device pci 18.4 off end # 8086 22c4 - I2C Port 4 + device pci 18.5 off end # 8086 22c5 - I2C Port 5 + device pci 18.6 off end # 8086 22c6 - I2C Port 6 + device pci 18.7 off end # 8086 22c7 - I2C Port 7 + device pci 1a.0 on end # 8086 2298 - Trusted Execution Engine + device pci 1b.0 on end # 8086 2284 - HD Audio + device pci 1c.0 on end # 8086 0000 - PCIe Root Port 1 + device pci 1c.1 on end # 8086 0000 - PCIe Root Port 2 + device pci 1c.2 on end # 8086 0000 - PCIe Root Port 3 + device pci 1c.3 on end # 8086 0000 - PCIe Root Port 4 + device pci 1e.0 off end # 8086 2286 - SIO - DMA + device pci 1e.3 off end # 8086 228a - HSUART 1 + device pci 1e.4 off end # 8086 228c - HSUART 2 + device pci 1f.0 on # 8086 229c - LPC bridge + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end # LPC Bridge + device pci 1f.3 on end # 8086 2292 - SMBus 0 + end +end diff --git a/src/mainboard/portwell/m107/dsdt.asl b/src/mainboard/portwell/m107/dsdt.asl new file mode 100644 index 0000000..3c62792 --- /dev/null +++ b/src/mainboard/portwell/m107/dsdt.asl @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2015-2018 Intel Corp. + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x05, /* DSDT revision: ACPI v5.0 */ + "COREv4", /* OEM id */ + "COREBOOT", /* OEM table id */ + 0x20110725 /* OEM revision */ +) +{ + /* Some generic macros */ + #include <acpi/platform.asl> + + /* global NVS and variables */ + #include <acpi/globalnvs.asl> + + #include <acpi/cpu.asl> + + Scope (_SB) { + Device (PCI0) + { + #include <acpi/southcluster.asl> + } + } + + /* Chipset specific sleep states */ + #include "acpi/sleepstates.asl" + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/portwell/m107/fadt.c b/src/mainboard/portwell/m107/fadt.c new file mode 100644 index 0000000..0479c97 --- /dev/null +++ b/src/mainboard/portwell/m107/fadt.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/acpi.h> +#include <string.h> + +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->model = 1; + fadt->preferred_pm_profile = PM_MOBILE; + + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + acpi_fill_in_fadt(fadt); + + fadt->iapc_boot_arch &= ~ACPI_FADT_8042; + + header->checksum = + acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/portwell/m107/gpio.c b/src/mainboard/portwell/m107/gpio.c new file mode 100644 index 0000000..3a3613c --- /dev/null +++ b/src/mainboard/portwell/m107/gpio.c @@ -0,0 +1,260 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "irqroute.h" +#include <soc/gpio.h> +#include <stdlib.h> + +/* South East Community */ +static const struct soc_gpio_map gpse_gpio_map[] = { + Native_M1,/* 00 MF_PLT_CLK0 */ + GPIO_NC, /* 01 PWM1 */ + GPIO_INPUT_NO_PULL, /* 02 MF_PLT_CLK1, RAMID2 */ + GPIO_NC, /* 03 MF_PLT_CLK4 */ + GPIO_NC, /* 04 MF_PLT_CLK3 */ + GPIO_NC, /* PWM0 05 */ + GPIO_NC, /* 06 MF_PLT_CLK5 */ + GPIO_NC, /* 07 MF_PLT_CLK2 */ + GPIO_NC, /* 15 SDMMC2_D3_CD_B */ + Native_M1, /* 16 SDMMC1_CLK */ + NATIVE_PU20K(1), /* 17 SDMMC1_D0 */ + GPIO_NC, /* 18 SDMMC2_D1 */ + GPIO_NC, /* 19 SDMMC2_CLK */ + NATIVE_PU20K(1),/* 20 SDMMC1_D2 */ + GPIO_NC, /* 21 SDMMC2_D2 */ + GPIO_NC, /* 22 SDMMC2_CMD */ + NATIVE_PU20K(1), /* 23 SDMMC1_CMD */ + NATIVE_PU20K(1), /* 24 SDMMC1_D1 */ + GPIO_NC, /* 25 SDMMC2_D0 */ + NATIVE_PU20K(1), /* 26 SDMMC1_D3_CD_B */ + NATIVE_PU20K(1), /* 30 SDMMC3_D1 */ + Native_M1, /* 31 SDMMC3_CLK */ + NATIVE_PU20K(1), /* 32 SDMMC3_D3 */ + NATIVE_PU20K(1), /* 33 SDMMC3_D2 */ + NATIVE_PU20K(1), /* 34 SDMMC3_CMD */ + NATIVE_PU20K(1), /* 35 SDMMC3_D0 */ + NATIVE_PU20K(1), /* 45 MF_LPC_AD2 */ + NATIVE_PU20K(1), /* 46 LPC_CLKRUNB */ + NATIVE_PU20K(1), /* 47 MF_LPC_AD0 */ + Native_M1, /* 48 LPC_FRAMEB */ + Native_M1, /* 49 MF_LPC_CLKOUT1 */ + NATIVE_PU20K(1), /* 50 MF_LPC_AD3 */ + Native_M1, /* 51 MF_LPC_CLKOUT0 */ + NATIVE_PU20K(1), /* 52 MF_LPC_AD1 */ + Native_M1,/* SPI1_MISO */ + Native_M1, /* 61 SPI1_CS0_B */ + Native_M1, /* SPI1_CLK */ + NATIVE_PU20K(1), /* 63 MMC1_D6 */ + Native_M1, /* 62 SPI1_MOSI */ + NATIVE_PU20K(1), /* 65 MMC1_D5 */ + GPIO_NC, /* 66 SPI1_CS1_B */ + NATIVE_PU20K(1), /* 67 MMC1_D4_SD_WE */ + NATIVE_PU20K(1), /* 68 MMC1_D7 */ + GPIO_NC, /* 69 MMC1_RCLK */ + Native_M1, /* 75 GPO USB_OC1_B */ + Native_M1, /* 76 PMU_RESETBUTTON_B */ + GPIO_NC, /* 77 GPIO_ALERT */ + Native_M1, /* 78 SDMMC3_PWR_EN_B */ + Native_M1, /* 79 GPI ILB_SERIRQ */ + Native_M1, /* 80 USB_OC0_B */ + NATIVE_INT_PU20K(1, L1), /* 81 SDMMC3_CD_B */ + Native_M1, /* 82 SPKR */ + Native_M1, /* 83 SUSPWRDNACK */ + SPARE_PIN, /* 84 spare pin */ + Native_M1, /* 85 SDMMC3_1P8_EN */ + GPIO_END +}; + + +/* South West Community */ +static const struct soc_gpio_map gpsw_gpio_map[] = { + Native_M1, /* 00 FST_SPI_D2 */ + Native_M1, /* 01 FST_SPI_D0 */ + Native_M1, /* 02 FST_SPI_CLK */ + Native_M1, /* 03 FST_SPI_D3 */ + Native_M1, /* 04 FST_SPI_CS1_B */ + Native_M1, /* 05 FST_SPI_D1 */ + Native_M1, /* 06 FST_SPI_CS0_B */ + Native_M1, /* 07 FST_SPI_CS2_B */ + GPIO_NC, /* 15 UART1_RTS_B */ + GPIO_NC, /* 16 UART1_RXD */ + GPIO_NC, /* 17 UART2_RXD */ + GPIO_NC, /* 18 UART1_CTS_B */ + GPIO_NC, /* 19 UART2_RTS_B */ + GPIO_NC, /* 20 UART1_TXD */ + GPIO_NC, /* 21 UART2_TXD */ + GPIO_NC, /* 22 UART2_CTS_B */ + Native_M2, /* 30 MF_HDA_CLK */ + Native_M2, /* 31 MF_HDA_RSTB */ + Native_M2, /* 32 MF_HDA_SDI0 */ + Native_M2, /* 33 MF_HDA_SDO */ + GPIO_NC, /* 34 MF_HDA_DOCKRSTB */ + Native_M2, /* 35 MF_HDA_SYNC */ + GPIO_NC, /* 36 MF_HDA_SDI1 */ + GPIO_NC, /* 37 MF_HDA_DOCKENB */ + GPIO_NC, /* 45 I2C5_SDA */ + GPIO_NC, /* 46 I2C4_SDA */ + GPIO_INPUT_NO_PULL, /* 47 I2C6_SDA SD_WP_1P8*/ + GPIO_NC, /* 48 I2C5_SCL */ + GPIO_NC, /* 49 I2C_NFC_SDA */ + GPIO_NC, /* 50 I2C4_SCL */ + GPIO_NC, /* 51 I2C6_SCL */ + GPIO_NC, /* 52 I2C_NFC_SCL */ + GPIO_NC, /* 60 I2C1_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 61 I2C0_SDA */ + GPIO_NC, /* 62 I2C2_SDA */ + GPIO_NC, /* 63 I2C1_SCL */ + GPIO_NC, /* 64 I2C3_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 65 I2C0_SCL */ + GPIO_NC, /* 66 I2C2_SCL */ + GPIO_NC, /* 67 I2C3_SCL */ + GPIO_NC, /* 75 SATA_GP0 */ + GPIO_NC, /* 76 GPI SATA_GP1 */ + Native_M1, /* 77 SATA_LEDN */ + GPIO_NC, /* 78 SATA_GP2 */ + Native_M1, /* 79 MF_SMB_ALERT_N */ + GPIO_INPUT_NO_PULL, /* 80 SATA_GP3, MMC1_RST */ + Native_M1, /* 81 MF_SMB_CLK */ + Native_M1, /* 82 MF_SMB_DATA */ + Native_M1, /* 90 PCIE_CLKREQ0B */ + Native_M1, /* 91 PCIE_CLKREQ1B */ + GPIO_NC, /* 92 GP_SSP_2_CLK */ + Native_M1, /* 93 PCIE_CLKREQ2B */ + GPIO_NC, /* 94 GP_SSP_2_RXD */ + Native_M1, /* 93 PCIE_CLKREQ3B */ + GPIO_NC, /* 96 GP_SSP_2_FS */ + GPIO_NC, /* 97 GP_SSP_2_TXD */ + GPIO_END +}; + + +/* North Community */ +static const struct soc_gpio_map gpn_gpio_map[] = { + GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data, + UNMASK_WAKE, SCI), /* 00 GPIO_DFX0 SMC_EXTSMI_N */ + GPIO_NC, /* 01 GPIO_DFX3 */ + GPIO_NC, /* 02 GPIO_DFX7 */ + GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data, + UNMASK_WAKE, SCI), /* 03 GPIO_DFX1 PM_THRM_N */ + GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data, + UNMASK_WAKE, SCI), /* 04 GPIO_DFX5 LID_N */ + GPIO_NC, /* 05 GPIO_DFX4 */ + GPIO_NC, /* 06 GPIO_DFX8 */ + GPIO_NC, /* 07 GPIO_DFX2 */ + GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data, + UNMASK_WAKE, SCI), /* 08 GPIO_DFX6 WAKE1_N */ + GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data, + UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */ + GPIO_NC, /* 16 SEC_GPIO_SUS10 */ + GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), + /* 17 GPIO_SUS3 */ + GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + /* 18 GPIO_SUS7 */ + GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + /* 19 GPIO_SUS1 */ + GPIO_NC, /* 20 GPIO_SUS5 */ + GPIO_NC, /* 21 SEC_GPIO_SUS11 */ + GPIO_NC, /* 22 GPIO_SUS4 */ + GPIO_NC, /* 23 SEC_GPIO_SUS8 */ + Native_M6, /* 24 GPIO_SUS2 */ + GPIO_INPUT_PU_5K,/* 25 GPIO_SUS6 */ + Native_M1, /* 26 CX_PREQ_B */ + GPIO_NC, /* 27 SEC_GPIO_SUS9 */ + Native_M1, /* 30 TRST_B */ + Native_M1, /* 31 TCK */ + GPIO_SKIP, /* 32 PROCHOT_B */ + GPIO_SKIP, /* 33 SVID0_DATA */ + Native_M1, /* 34 TMS */ + GPIO_NC, /* 35 CX_PRDY_B_2 */ + GPIO_NC, /* 36 TDO_2 */ + Native_M1, /* 37 CX_PRDY_B */ + GPIO_SKIP, /* 38 SVID0_ALERT_B */ + Native_M1, /* 39 TDO */ + GPIO_SKIP, /* 40 SVID0_CLK */ + Native_M1, /* 41 TDI */ + GPIO_NC, /* 45 GP_CAMERASB05 */ + GPIO_NC, /* 46 GP_CAMERASB02 */ + Native_M2, /* 47 GP_CAMERASB08 */ + GPIO_NC, /* 48 GP_CAMERASB00 */ + GPIO_NC, /* 49 GP_CAMERASBO6 */ + Native_M2, /* 50 GP_CAMERASB10 */ + GPIO_NC, /* 51 GP_CAMERASB03 */ + Native_M2, /* 52 GP_CAMERASB09 */ + GPIO_NC, /* 53 GP_CAMERASB01 */ + GPIO_NC, /* 54 GP_CAMERASB07 */ + Native_M2, /* 55 GP_CAMERASB11 */ + GPIO_NC, /* 56 GP_CAMERASB04 */ + GPIO_NC, /* 60 PANEL0_BKLTEN */ + Native_M1, /* 61 HV_DDI0_HPD */ + GPIO_NC, /* 62 HV_DDI2_DDC_SDA */ + GPIO_NC, /* 63 PANEL1_BKLTCTL */ + Native_M1, /* 64 HV_DDI1_HPD */ + Native_M1, /* 65 PANEL0_BKLTCTL */ + NATIVE_PU20K(1), /* 66 HV_DDI0_DDC_SDA */ + GPIO_NC, /* 67 HV_DDI2_DDC_SCL */ + NATIVE_TX_RX_EN, /* 68 HV_DDI2_HPD */ + GPIO_NC, /* 69 PANEL1_VDDEN */ + GPIO_NC, /* 70 PANEL1_BKLTEN */ + NATIVE_PU20K(1), /* 71 HV_DDI0_DDC_SCL */ + GPIO_NC, /* 72 PANEL0_VDDEN */ + GPIO_END +}; + + +/* East Community */ +static const struct soc_gpio_map gpe_gpio_map[] = { + Native_M1, /* 00 PMU_SLP_S3_B */ + GPIO_NC, /* 01 PMU_BATLOW_B */ + Native_M1, /* 02 SUS_STAT_B */ + Native_M1, /* 03 PMU_SLP_S0IX_B */ + Native_M1, /* 04 PMU_AC_PRESENT */ + Native_M1, /* 05 PMU_PLTRST_B */ + Native_M1, /* 06 PMU_SUSCLK */ + GPIO_NC, /* 07 PMU_SLP_LAN_B */ + Native_M1, /* 08 PMU_PWRBTN_B */ + Native_M1, /* 09 PMU_SLP_S4_B */ + NATIVE_FUNC(M1, P_1K_H, NA), /* 10 PMU_WAKE_B */ + GPIO_NC, /* 11 PMU_WAKE_LAN_B */ + GPIO_NC, /* 15 MF_GPIO_3 */ + GPIO_NC, /* 16 MF_GPIO_7 */ + GPIO_NC, /* 17 MF_I2C1_SCL */ + GPIO_NC, /* 18 MF_GPIO_1 */ + GPIO_NC, /* 19 MF_GPIO_5 */ + GPIO_NC, /* 20 MF_GPIO_9 */ + GPIO_NC, /* 21 MF_GPIO_0 */ + GPIO_INPUT_PU_20K, /* 22 MF_GPIO_4 */ + GPIO_NC, /* 23 MF_GPIO_8 */ + GPIO_NC, /* 24 MF_GPIO_2 */ + GPIO_NC, /* 25 MF_GPIO_6 */ + GPIO_NC, /* 26 MF_I2C1_SDA */ + GPIO_END +}; + + +static struct soc_gpio_config gpio_config = { + /* BSW */ + .north = gpn_gpio_map, + .southeast = gpse_gpio_map, + .southwest = gpsw_gpio_map, + .east = gpe_gpio_map +}; + +struct soc_gpio_config *mainboard_get_gpios(void) +{ + + return &gpio_config; +} diff --git a/src/mainboard/portwell/m107/hda_verb.c b/src/mainboard/portwell/m107/hda_verb.c new file mode 100644 index 0000000..868e524 --- /dev/null +++ b/src/mainboard/portwell/m107/hda_verb.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[0] = {}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/portwell/m107/irqroute.c b/src/mainboard/portwell/m107/irqroute.c new file mode 100644 index 0000000..79dc8d6 --- /dev/null +++ b/src/mainboard/portwell/m107/irqroute.c @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "irqroute.h" + +DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/portwell/m107/irqroute.h b/src/mainboard/portwell/m107/irqroute.h new file mode 100644 index 0000000..ab570b9 --- /dev/null +++ b/src/mainboard/portwell/m107/irqroute.h @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/irq.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> + +/* + *IR02h GFX INT(A) - PIRQ A + *IR10h EMMC INT(ABCD) - PIRQ DEFG + *IR11h SDIO INT(A) - PIRQ B + *IR12h SD INT(A) - PIRQ C + *IR13h SATA INT(A) - PIRQ D + *IR14h XHCI INT(A) - PIRQ E + *IR15h LP Audio INT(A) - PIRQ F + *IR17h MMC INT(A) - PIRQ F + *IR18h SIO INT(ABCD) - PIRQ BADC + *IR1Ah TXE INT(A) - PIRQ F + *IR1Bh HD Audio INT(A) - PIRQ G + *IR1Ch PCIe INT(ABCD) - PIRQ EFGH + *IR1Dh EHCI INT(A) - PIRQ D + *IR1Eh SIO INT(ABCD) - PIRQ BDEF + *IR1Fh LPC INT(ABCD) - PIRQ HGBC + */ +#define PCI_DEV_PIRQ_ROUTES \ + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(MMC_DEV, D, E, F, G), \ + PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \ + PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(PCIE_DEV, E, F, G, H), \ + PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \ + PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C) + +/* + * Route each PIRQ[A-H] to a PIC IRQ[0-15] + * Reserved: 0, 1, 2, 8, 13 + * PS2 keyboard: 12 + * ACPI/SCI: 9 + * Floppy: 6 + */ +#define PIRQ_PIC_ROUTES \ + PIRQ_PIC(A, 11), \ + PIRQ_PIC(B, 5), \ + PIRQ_PIC(C, 5), \ + PIRQ_PIC(D, 11), \ + PIRQ_PIC(E, 11), \ + PIRQ_PIC(F, 5), \ + PIRQ_PIC(G, 11), \ + PIRQ_PIC(H, 11) diff --git a/src/mainboard/portwell/m107/mainboard.c b/src/mainboard/portwell/m107/mainboard.c new file mode 100644 index 0000000..a35bdd4 --- /dev/null +++ b/src/mainboard/portwell/m107/mainboard.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <console/console.h> + +/* + * mainboard_enable is executed as first thing after + * enumerate_buses(). + */ +static void mainboard_enable(struct device *dev) +{ +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/portwell/m107/onboard.h b/src/mainboard/portwell/m107/onboard.h new file mode 100644 index 0000000..063b919 --- /dev/null +++ b/src/mainboard/portwell/m107/onboard.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#include "irqroute.h" + +/* SD CARD gpio */ +#define SDCARD_CD 81 /* Not used */ + +#define ITE8528_CMD_PORT 0x6E +#define ITE8528_DATA_PORT 0x6F +#endif diff --git a/src/mainboard/portwell/m107/romstage.c b/src/mainboard/portwell/m107/romstage.c new file mode 100644 index 0000000..cd1826f --- /dev/null +++ b/src/mainboard/portwell/m107/romstage.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbfs.h> +#include <console/console.h> +#include <lib.h> +#include <soc/romstage.h> +#include <chip.h> + +/* + * First call into mainboard. + */ +void mainboard_romstage_entry(struct romstage_params *params) +{ + struct pei_data *ps = params->pei_data; + char buf[32]; + + post_code(0x31); + + strcpy(buf, CONFIG_MAINBOARD_SPD0_FILE_NAME); + ps->spd_data_ch0 = cbfs_boot_map_with_leak(buf, CBFS_TYPE_SPD, NULL); + ps->spd_ch0_config = 1; /* Memory down */ + ps->spd_ch1_config = 2; /* Disabled */ + + /* Initialize memory */ + romstage_common(params); +} + +void mainboard_memory_init_params(struct romstage_params *params, + MEMORY_INIT_UPD *memory_params) +{ + memory_params->PcdMemoryTypeEnable = MEM_DDR3; + memory_params->PcdMemorySpdPtr = (u32)params->pei_data->spd_data_ch0; + memory_params->PcdMemChannel0Config = params->pei_data->spd_ch0_config; + memory_params->PcdMemChannel1Config = params->pei_data->spd_ch1_config; +} diff --git a/src/mainboard/portwell/m107/smihandler.c b/src/mainboard/portwell/m107/smihandler.c new file mode 100644 index 0000000..ca4081f --- /dev/null +++ b/src/mainboard/portwell/m107/smihandler.c @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <soc/nvs.h> +#include <soc/pm.h> + +/* The wake gpio is SUS_GPIO[0]. */ +#define WAKE_GPIO_EN SUS_GPIO_EN0 + +int mainboard_io_trap_handler(int smif) +{ + switch (smif) { + case 0x99: + printk(BIOS_DEBUG, "Sample\n"); + smm_get_gnvs()->smif = 0; + break; + default: + return 0; + } + + /* + * On success, the IO Trap Handler returns 0 + * On failure, the IO Trap Handler returns a value != 0 + * + * For now, we force the return value to 0 and log all traps to + * see what's going on. + */ + //gnvs->smif = 0; + return 1; +} + +/* + * The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that + * this includes the enable bits in the lower 16 bits. + */ +void mainboard_smi_gpi(uint32_t alt_gpio_smi) +{ +} + +void mainboard_smi_sleep(uint8_t slp_typ) +{ + /* Disable USB charging if required */ + switch (slp_typ) { + case ACPI_S3: + /* Enable wake pin in GPE block. */ + enable_gpe(WAKE_GPIO_EN); + break; + case ACPI_S5: + break; + } + +} + +int mainboard_smi_apmc(uint8_t apmc) +{ + switch (apmc) { + case APM_CNT_ACPI_ENABLE: + break; + case APM_CNT_ACPI_DISABLE: + break; + } + return 0; +} diff --git a/src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex b/src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex new file mode 100644 index 0000000..f5876f8 --- /dev/null +++ b/src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex @@ -0,0 +1,244 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2018 Eltan B.V. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +# +# 8 Gb DDR3 (1600 MHz 11-11-11) Samsung K4B8G1646D-MYK0 +# +# DUAL DIE +# + +# 2 * 256Mx16 ( 8 bank, 16 Rows, 10 Col, 1KB page size ) +# 5-6-7-8-9-10-11-12-13 +# DDR3L-1600 +# tCk 1.25ns +# tRCD 13.75ns +# tRP 13.75ns +# tRAS 35ns +# tRC 48.75ns +# CL-tRCD-tRP 11-11-11 + +# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage +# bits[3:0]: 3 = 384 SPD Bytes Used +# bits[6:4]: 1 = 256 SPD Bytes Total +# bit7 : 0 = CRC covers bytes 0 ~ 128 +23 + +# 1 SPD Revision +# 0x10 = Revision 1.0 +10 + +# 2 Key Byte / DRAM Device Type +# bits[7:0]: 0x0c = DDR3 SDRAM +0B + +# 3 Key Byte / Module Type +# bits[3:0]: 3 = SODIMM +# bits[6:4]: 0 = Not hybrid +# bits[7]: 0 = Not hybrid +03 + +# 4 SDRAM CHIP Density and Banks +# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip +# bits[6:4]: 0 = 3 (8 banks) +# bits[7]: reserverd +04 + +# 5 SDRAM Addressing +# bits[2:0]: 1 = 10 Column Address Bits +# bits[5:3]: 4 = 16 Row Address Bits +# bits[7:6]: 0 = reserved +21 + +# 6 Module Nominal Voltage +# bits[0]: 0 = 1.5V operable +# bits[1]: 1 = 1.35V operable +# bits[2]: 0 = NOT 1.25V operable +# bits[7:3]: reserved +02 + +# 7 Module Organization +# bits[2:0]: 010 = 16 bits SDRAM device +# bits[5:3]: 001 = 2 ranks +# bits[7:6]: reserved +0A + +# 8 Module Memory Bus width +# bits[2:0]: 3 = 64 bits pirmary bus width +# bits[4:3]: 0 = 0 bits bus witdth extension +# bits[7:5]: reserved +03 + +# 9 Fine Timebase (FTB) dividend / divisor +# bits[3:0]: 1 = Divisor +# bits[7:4]: 1 = Dividend +11 + +# 10 Medium Timebase (MTB) dividend +# bits[7:0]: 0 = 1 (timebase 0.125ns) +01 + +# 11 Medium Timebase (MTB) divisor +# bits[7:0]: 8 (timebase 0.125ns) +08 + +# 12 SDRAM Minimum cycle time (tCKmin) +# bits[7:0]: 10 (10 * 0x125 1 = 8 bits (Device Width) +# bits[5:4]: 0 = 1 Package rank +# bits[6]: 0 = Symmetrical (rank mix) +# bits[7]: 0 = reserved +0A + +# 13 Reserved +00 + +# 14 CAS Latencies supported, Least Significate Byte +FE + +# 15 CAS Latencies supported, Most Significate Byte +00 + +# 16 Minimum CAS Latency Time (tAAmin) +# 0x69 tAA = 13.125ns (offset 00) DDR3-1600K downbin +69 + +# 17 Minimum Write Recovery Time (tWRmin) +78 + +# 18 Minimum RAS to CAS Delay Time (tRCDmin) +# 0x69 tAA = 13.125ns (offset 00) DDR3-1600K downbin +69 + +# 19 Minimum Row Active to Row Active Delay Time (tRRDmin) +# 60 tRRD = 6.0ns DDR3-1600, 1KB +30 + +# 20 Minimum Row Precharge Delay Time (tRPmin) +# 0x69 tAA = 13.125ns (offset 00) DDR3-1600K downbin +69 + +# 21 Upper Nibble for tRAS and tRC +# 7:0 tRC, 3:0 tRAS +11 + +# 22 Minimum Active to Precharge Delay Time (tRASmin), Least Significant byte +18 + +# 23 Minimum Active to Precharge Delay Time (tRCmin), Most Significant byte +# 0x181 tRC = 48.125ns (offset 00) DDR3-1600K downbin +81 + +# 24 Minimum Refresh Recovery Delay time (tRFCmin), Least Significant byte +# 0x680 tRFC = 208ns DDR3-1600K downbin +80 + +# 25 Minimum Refresh Recovery Delay time (tRFCmin), Most Significant byte +# 0x680 tRFC = 208ns DDR3-1600K downbin +06 + +# 26 tWTRmin +3C + +# 27 tRTPmin +3C + +# 28 Upper Nibble for tFAW +# Upper 0x140 tRAW = 40ns DDR3-1600K downbin +01 + +# 29 tFAWmin Lower +# 0x140 tRAW = 40ns DDR3-1600K downbin +40 + +# 30 SDRAM Optional Features +# byte [7]: 1 = DLL-Off Mode support +# byte [1]: 1 = RZQ/7 is supported +# byte [0]: 1 = RZQ/6 is support +# +83 + +# 31 Thermal options +# byte [2]: 1 = Auto Self Refresh (ASR) is supported +04 + +# 32 Module Thermal support +00 + +# 33 SDRAM device type +# byte [6:4] 100 = 7 die +# byte [1:0] 1 = multi load stack +41 + +# 34 Fine tCKmin +00 + +# 35 Fine tAAmin +00 + +# 36 Fine tRCDmin +00 + +# 37 Fine tRPmin +00 + +# 38 Fine tRCmin +00 + +# 39-59 reserved, general section +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 + +# 60-116 Module specific section +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 + +# 117-118 Module Manufacturer +80 CE + +# 119 Module Manufacturing Location +01 + +# 120-121 Module Manufacturing Date +12 1B + +# 122-125 Module Serial number +00 00 00 00 + +# 126-127 SPD CRC +00 00 + +# 128-145 Module Part number +4B 34 42 38 47 31 36 34 36 44 2D 4D 59 4B 30 20 +20 20 + +# 145-146 Module revision code +00 00 + +# 148-149 DRAM Manufacturer ID code +80 CE + +# 150-175 Manufacturer Specific Data +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 + +# 176-255 Open for Customer Use + +# 175 - 255 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/portwell/m107/w25q64.c b/src/mainboard/portwell/m107/w25q64.c new file mode 100644 index 0000000..63665c1 --- /dev/null +++ b/src/mainboard/portwell/m107/w25q64.c @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/spi.h> +#include <string.h> + +/* + * SPI lockdown configuration W25Q64FW. + */ +#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ +#define SPI_OPTYPE_0 0x01 /* Write, no address */ + +#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ +#define SPI_OPTYPE_1 0x03 /* Write, address required */ + +#define SPI_OPMENU_2 0x03 /* READ: Read Data */ +#define SPI_OPTYPE_2 0x02 /* Read, address required */ + +#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ +#define SPI_OPTYPE_3 0x00 /* Read, no address */ + +#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ +#define SPI_OPTYPE_4 0x03 /* Write, address required */ + +#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ +#define SPI_OPTYPE_5 0x00 /* Read, no address */ + +#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ +#define SPI_OPTYPE_6 0x03 /* Write, address required */ + +#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ +#define SPI_OPTYPE_7 0x02 /* Read, address required */ + +#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ +#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ + (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ + (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ + (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0)) +#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ + (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0)) +#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ + (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0)) +#define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB) + +static const struct spi_config spi_config = { + .preop = SPI_OPPREFIX, + .optype = SPI_OPTYPE, + .opmenu = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER }, + .lvscc = SPI_VSCC, + .uvscc = SPI_VSCC, +}; + +int mainboard_get_spi_config(struct spi_config *cfg) +{ + memcpy(cfg, &spi_config, sizeof(*cfg)); + + return 0; +}