Vladimir Serbinenko (phcoder@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6689
-gerrit
commit 086dd5c6f562657ddc8d981e72f84d8621688aad Author: Vladimir Serbinenko phcoder@gmail.com Date: Sat Aug 16 14:18:21 2014 +0200
gm45: Declare BIOS memory as RAM.
So it's in line with other boards and those addresses are cached for faster access.
Change-Id: I7794d75ef1e3ceea6b2a4acba01e4af5d1f005f5 Signed-off-by: Vladimir Serbinenko phcoder@gmail.com --- src/northbridge/intel/gm45/northbridge.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 42561e4..7a4b038 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -34,14 +34,12 @@ #include "gm45.h" #include "arch/acpi.h"
-/* Reserve everything between A segment and 1MB: +/* Reserve segments A and B: * * 0xa0000 - 0xbffff: legacy VGA - * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel) - * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI */ static const int legacy_hole_base_k = 0xa0000 / 1024; -static const int legacy_hole_size_k = 384; +static const int legacy_hole_size_k = 128;
static int decode_pcie_bar(u32 *const base, u32 *const len) {