[coreboot-gerrit] Change in coreboot[master]: soc/intel/cnl: Fix `PcieClkSrcUsage` setting

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39795 )

Change subject: soc/intel/cnl: Fix `PcieClkSrcUsage` setting
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Patch Set 1:
> Patch Set 1:
>
> Yeah, sorry, the commit message was stale. That's why the original, vanished?
> change was [WIP]. The actual problem with the for-loop is that it replaces
> Clock Source 0 with garbage, i.e. you can't configure 0 for any board because
> somebody took the weirdest shortcut, using the fact that unset devicetree
> options default to 0. But 0 is a valid value :-/

s/Clock Source 0/Clock Source for the first root port/