Attention is currently required from: Máté Kukri, Martin Roth, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55232 )
Change subject: [WIP] mb/dell: Add OptiPlex 7020 SFF port ......................................................................
Patch Set 1:
(8 comments)
Patchset:
PS1: I didn't review the obviously-WIP parts, but still left some comments.
File src/mainboard/dell/optiplex_7020/Kconfig:
https://review.coreboot.org/c/coreboot/+/55232/comment/09b39b48_2dd6144e PS1, Line 22: default 0x100000 Isn't it the default?
File src/mainboard/dell/optiplex_7020/acpi/platform.asl:
https://review.coreboot.org/c/coreboot/+/55232/comment/f28220dd_3fd99b28 PS1, Line 15: Device (PWRB) FADT flags make this unnecessary.
File src/mainboard/dell/optiplex_7020/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/55232/comment/644b0ab4_f82acbf4 PS1, Line 16: subsystemid 0x1028 0x05a5 Can be inherited, see other boards
https://review.coreboot.org/c/coreboot/+/55232/comment/17dcc062_c7ca7179 PS1, Line 57: device pci 1c.3 off end # TODO: what's this? : device pci 1c.4 off end # TODO: what's this? : device pci 1c.5 off end # TODO: what's this? More PCIe ports! Or is it that you don't know if they're actually used?
File src/mainboard/dell/optiplex_7020/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/55232/comment/0d01193e_c9f35c41 PS1, Line 20: Scope (_SB) : { : Device (PCI0) : { : #include <northbridge/intel/haswell/acpi/hostbridge.asl> : #include <southbridge/intel/lynxpoint/acpi/pch.asl> : } : } I usually write this as follows:
Device (_SB.PCI0) #include <northbridge/intel/haswell/acpi/hostbridge.asl> #include <southbridge/intel/lynxpoint/acpi/pch.asl> }
File src/mainboard/dell/optiplex_7020/gma-mainboard.ads:
https://review.coreboot.org/c/coreboot/+/55232/comment/e10c7365_37ef460e PS1, Line 11: -- TODO: Add DP ports to the list You can add all of them and look at libgfxinit logs with a DP display attached to see which one is which. Linux can also know via the VBT
File src/southbridge/intel/lynxpoint/early_pch.c:
https://review.coreboot.org/c/coreboot/+/55232/comment/d7105d0f_e33453da PS1, Line 72: pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0a01); You could set `gen1_dec` in the devicetree, or any other available `genX_dec`