build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39280 )
Change subject: soc/intel/tigerlake: Correct FSP log interface for JSL ......................................................................
Patch Set 3:
(3 comments)
https://review.coreboot.org/c/coreboot/+/39280/3/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/39280/3/src/soc/intel/tigerlake/chi... PS3, Line 197: *Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' line over 96 characters
https://review.coreboot.org/c/coreboot/+/39280/3/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params_jsl.c:
https://review.coreboot.org/c/coreboot/+/39280/3/src/soc/intel/tigerlake/rom... PS3, Line 73: /* UART configration */ 'configration' may be misspelled - perhaps 'configuration'?
https://review.coreboot.org/c/coreboot/+/39280/3/src/soc/intel/tigerlake/rom... PS3, Line 77: /* TraceHub configration */ 'configration' may be misspelled - perhaps 'configuration'?