Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34449 )
Change subject: soc/intel/common: Set controller state to active in GSPI init ......................................................................
Patch Set 3:
(7 comments)
https://review.coreboot.org/c/coreboot/+/34449/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34449/1//COMMIT_MSG@9 PS1, Line 9: Set the controller state to D0 during the GSPI sequence, : this ensures the controller is up and active.
Please use the full text width.
Done
https://review.coreboot.org/c/coreboot/+/34449/1/src/soc/intel/common/block/... File src/soc/intel/common/block/gspi/gspi.c:
https://review.coreboot.org/c/coreboot/+/34449/1/src/soc/intel/common/block/... PS1, Line 179: lpss_set_power_state(tree_dev, STATE_D0);
please, no spaces at the start of a line
Done
https://review.coreboot.org/c/coreboot/+/34449/1/src/soc/intel/common/block/... PS1, Line 179: lpss_set_power_state(tree_dev, STATE_D0)
gspi_early_bar_init() is getting called from bootblock/pch. […]
Done
https://review.coreboot.org/c/coreboot/+/34449/1/src/soc/intel/common/block/... PS1, Line 179:
Done
Done
https://review.coreboot.org/c/coreboot/+/34449/1/src/soc/intel/common/block/... PS1, Line 179: lpss_set_power_state(tree_dev, STATE_D0);
code indent should use tabs where possible
Done
https://review.coreboot.org/c/coreboot/+/34449/1/src/soc/intel/common/block/... PS1, Line 458: lpss_set_power_state((struct device*) dev, STATE_D0);
Done
Done
https://review.coreboot.org/c/coreboot/+/34449/2/src/soc/intel/common/block/... File src/soc/intel/common/block/gspi/gspi.c:
https://review.coreboot.org/c/coreboot/+/34449/2/src/soc/intel/common/block/... PS2, Line 455: devfn = gspi_soc_bus_to_devfn(dev->bus); : device = pcidev_path_on_root(devfn); : : /* Ensure controller is in D0 state */ : lpss_set_power_state(device, STATE_D0);
Thank you. Yes, I am considering doing it after the reset i.e line 480. […]
Done