[coreboot-gerrit] Change in coreboot[master]: sandybridge: fix when resources are added

[Aaron Durbin (Code Review)]

Aaron Durbin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41364 )

Change subject: sandybridge: fix when resources are added
......................................................................

sandybridge: fix when resources are added

Change-Id: I8a7081020be43da055b7de5a56dd97a7b5a9f09c
Signed-off-by: Aaron Durbin 
---
M src/northbridge/intel/sandybridge/northbridge.c
1 file changed, 8 insertions(+), 10 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/41364/1

diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index 7a6372c..7057151 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -99,7 +99,7 @@
    }
 }

-static void pci_domain_set_resources_sandybridge(struct device *dev)
+static void mc_read_resources_full(struct device *mch)
 {
    uint64_t tom, me_base, touud;
    uint32_t tseg_base, uma_size, tolud;
@@ -132,8 +132,6 @@
     * 14fe00000   5368MB TOUUD
     */

-	struct device *mch = pcidev_on_root(0, 0);
-
    /* Top of Upper Usable DRAM, including remap */
    touud  = pci_read_config32(mch, TOUUD + 4);
    touud <<= 32;
@@ -202,8 +200,8 @@
    printk(BIOS_INFO, "Available memory below 4GB: %lluM\n", tomk >> 10);

/* Report the memory regions */
-	ram_resource(dev, 3, 0, legacy_hole_base_k);
-	ram_resource(dev, 4, legacy_hole_base_k + legacy_hole_size_k,
+	ram_resource(mch, 3, 0, legacy_hole_base_k);
+	ram_resource(mch, 4, legacy_hole_base_k + legacy_hole_size_k,
    	    (tomk - (legacy_hole_base_k + legacy_hole_size_k)));

/*
@@ -212,13 +210,11 @@
     */
    touud >>= 10; /* Convert to KB */
    if (touud > 4096 * 1024) {
-		ram_resource(dev, 5, 4096 * 1024, touud - (4096 * 1024));
+		ram_resource(mch, 5, 4096 * 1024, touud - (4096 * 1024));
    	printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", (touud >> 10) - 4096);
    }

-	add_fixed_resources(dev, 6);
-
-	assign_resources(dev->link_list);
+	add_fixed_resources(mch, 6);
 }

static const char *northbridge_acpi_name(const struct device *dev)
@@ -243,7 +239,7 @@
  */
 static struct device_operations pci_domain_ops = {
    .read_resources    = pci_domain_read_resources,
-	.set_resources     = pci_domain_set_resources_sandybridge,
+	.set_resources     = pci_domain_set_resources,
    .scan_bus          = pci_domain_scan_bus,
    .write_acpi_tables = northbridge_write_acpi_tables,
    .acpi_name         = northbridge_acpi_name,
@@ -261,6 +257,8 @@
    	struct resource *resource = new_resource(dev, PCIEXBAR);
    	mmconf_resource_init(resource, pcie_config_base, buses);
    }
+
+	mc_read_resources_full(dev);
 }

static void northbridge_dmi_init(struct device *dev)